Ever since I can remember, and I’ve been in EDA since the early 80’s, new process development has largely focused on the latest nodes. Trailing nodes were quickly put into support mode. New nodes benefited the most from static and dynamic voltage reduction efforts, as well as improvements in flows and performance. Only a small number of niche processes, usually produced by smaller captive fabs, were tuned over time for improvements. But the IoT has changed this.
With projected volumes for IoT chips in the billions, foundries, EDA and IP vendors have put a new emphasis on revisiting their offering for larger nodes. The biggest motivation for this is the need for lower power and the proliferation of wireless. When we say lower power, it’s not about needing fewer cooling fans, its about running for months on solar power, or making a wearable last for weeks before it needs to be recharged.
For wearables, using a larger battery is not an option. A typical wearable LiPo battery might have less than 20 milliamp-hours at 3.7V. Sleep modes need to be in the uA, not milliamp range. Every trick in the book is needed: voltage Islands, power islands, low leakage libraries, sub threshold operating voltages.
Apparently TSMC has been thinking about these issues for a while and concluded that updating processes alone will not solve the power problems faced by new products. So TSMC has announced the development of IoT platforms with several of their OIP partners. For its part TSMC is rolling out ultra low power (ULP) versions of its 0.18u, 90nm, 55nm, 40nm and 28nm processes. Several of them will come with embedded flash and the ability to support radio design.
TSMC expects the ULP processes to reduce operating voltages by 20% to 30%. That combined with standby power reductions promises to offer 2X to 10X increases in battery life.
TSMC has announced that the following partners are participating:
ARM – IoT subsystems for the Cortex-M and Cordio radio IP. Running on the 55nm ULP process, they can run below one-volt, saving significant power.
Cadence – Also targeting 55nm ULP, they offer Tensilica Fusion DSP’s for sensor and peripheral interfaces operating at optimal power levels. Tensilica cores are available for WiFi/IoT connectivity for wearables and other IoT applications. 40ULP and 28ULP are also available.
Dolphin Integration – Bringing ultra low power methodologies and flows for designing ultra low power designs that include voltage and power islands. They are providing tools to effectively reduce dynamic and static power for designs targeted by the TSMC partnership.
Imagination – IP for ultra low power designs. They are providing processor cores, wireless and other ancillary functions implemented as reference IoT subsystems. Imagination offers comprehensive IP for building a large number of IoT applications.
Synopsys – Working on an integrated IoT platform on TSMC’s 40nm ULP process. This will include a broad range of DesignWare IP. The highlights are the ultra low power ARC EM5D processor core, power and area optimized libraries, memory compilers, NVM as well as a number of IO and sensing blocks.
All of this represents a large commitment on the part of TSMC and their partners to create the processes and flow enablers necessary to fulfill projected design and volume demands fron the explosive growth of ultra low power connected designs for the IoT.
For more information on applications for different process nodes look on their site.Share this post via: