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3D NAND Myths and Realities

3D NAND Myths and Realities
by Scotten Jones on 06-30-2017 at 9:00 am

For many year 2D NAND drove lithography for the semiconductor industry with the smallest printed dimensions and yearly shrinks. As 2D NAND shrunk down to the mid-teens nodes, 16nm, 15nm and even 14nm, the cells became so small that there were only a few electrons in each cell and cross-talk issues made further shrinks very difficult and uneconomical.

As 2D NAND issues were growing, the industry was working on 3D NAND. We are now seeing a rapid ramp of 3D NAND with 3D bit production crossing over to exceed 2D bit production. In this article, we will examine 3D NAND technology and compare 3D NAND to 2D NAND costs.

3D NAND Processes
Early pioneering work from Toshiba and Samsung on 3D NAND led to two major competing 3D NAND technologies.

Toshiba developed a process they called Bit Cost Scalable (BiCS). In the BiCS process a gate-first approach is taken by depositing alternating layers of oxide (SiO) and polysilicon (pSi). A channel hole is then formed through the layer stack and filled with oxide-nitride-oxide (ONO) and pSi. Photoresist is deposited and through a successive set of etches, photoresist trims and etches a stair-step for interconnect is formed. Finally, a slot is etched and filled with oxide. See figure 1.

Figure 1. BiCS process.

Samsung developed an alternate Terabit Cell Array Transistor (TCAT) process. TCAT is a gate-last approach where alternating layers of oxide and nitride are deposited. A channel is then formed through the layers and filled with ONO and pSi. Stair-step formation then takes place similar to BiCS. Finally, a slot is etched down through the layers and nitride layers are stripped out, aluminum oxide (AlO), titanium nitride (TiN) and tungsten (W) are deposited and etched-back and finally the slot is filled with W. See figure 2.

Figure 2. TCAT process.

Both processes result in charge trap memory cells.

As can be seen from the preceding discussion and figures, the two processes are fundamentally different with BiCS using a gate-first approach with pSi word-lines and TCAT using a gate-last approach with W word-lines.

For a long time, there were rumors in the industry that Toshiba couldn’t make BiCS work and Toshiba’s parts in production are essentially copies of the TCAT process, although Toshiba still call them BiCS.

Intel-Micron have taken a different route similar to BiCS except that they create floating gates.

Capital Cost
I have seen many comments from people who see graphs like the one from Micron shown in figure 3 and go on to talk about the 3 to 5x higher capital costs for 3D NAND over 2D NAND. That isn’t what this graph says at all! What this graph says is converting from a 2D NAND node to a 3D NAND node is 3 to 5x the cost of converting from a 2D NAND to a new 2D NAND node.

Figure 3. Micron 2D NAND to 3D NAND conversion costs.

2D NAND is a lithography dominated process that for sub 20nm nodes requires multiple quadruple pattering steps. Moving from one node to the next node is primarily driven by improved lithography tools. When upgrading lithography tools typically the current tools are traded-in towards the improved tools resulting in reduced transition costs.

3D NAND on the other hand is dominated by depositions and etches with specialized tools required for the 3D memory stacks. Lithography is not a 3D NAND driver with at most one double pattering step in a 3D NAND process flow. There are however multiple high aspect ratio etch steps with etch times as high as 30 to 60 minutes per wafer!

To explore this further it is interesting to examine the capital requirements for greenfield fabs for 2D and 3D NAND. My company, IC Knowledge LLC produces the most widely used cost modeling tools in the semiconductor industry. Our Strategic Cost Model produces detailed equipment set requirements for 2D and 3D NAND processes. Before comparing greenfield fabs, figure 4. presents 2D to 3D NAND transition costs based on Samsung processes.

Figure 4. 2D NAND to 3D NAND Conversion Costs.
IC Knowledge – Strategic Cost Model.

From figure 4 we can see that depending on the process conversion specifics, we see a 3 to 5x conversion cost similar to figure 3.

However, if we simulate the cost to build a greenfield 2D NAND fab versus greenfield 3D NAND fabs we see a completely different picture, 3D capital costs are slightly lower than 2D capital costs! See figure 5.

Figure 5. Greenfield Fab capital costs.
IC Knowledge – Strategic Cost Model.

Wafer Cost
Similar to the capital costs we believe there is a lot of confusion around wafer costs. Figure 6 compares 2D – 16nm wafer costs for Samsung’s line 12 fab to 3D – 64-layer wafer costs in Samsung’s Xian fab.

Figure 6. 2D versus 3D NAND wafers costs for upgraded facilities.
IC Knowledge – Strategic Cost Model.

Line 12 came on-line in 2003 and has been through many upgrades so that significant parts of the equipment set are now fully depreciated. The Xian fab on the other hand came on-line in 2014 and all the equipment is still depreciating. If we compare wafer cost for greenfield 2D and 3D NAND fabs once again a different picture emerges. See figure 7.

Figure 7. 2D NAND versus 3D NAND wafers costs for a greenfield fab.
IC Knowledge – Strategic Cost Model.

Bit Density
Dividing the number of bits in a NAND device by the die size we can calculate a bits/mm[SUP]2[/SUP] metric for various devices. AT ISSCC this year Samsung published a paper entitled ” A 512Gb 3b/cell 64-Stacked WL 3D V-NAND Flash Memory” in session 11. From that paper, we can now compare bit density all the way up through 64-layer 3D NAND to 2D NAND. The following table illustrates the values for Samsung (all devices are 3 bits/cell).

[TABLE] align=”center” class=”cms_table_grid” style=”width: 300px”
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Device
| class=”cms_table_grid_td” | Bit density
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 2D – 16nm
| class=”cms_table_grid_td” | 1.11
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 3D – 32-layer
| class=”cms_table_grid_td” | 1.86
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 3D – 48-layer
| class=”cms_table_grid_td” | 2.56
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | 3D – 64-layer
| class=”cms_table_grid_td” | 3.97

Table 1. Samsung NAND bit density.

From table 1. it can be seen that bit density for 3D NAND has far surpassed 2D NAND with 64-layer devices over 3x the density of 2D – 16nm!

To-date 3D NAND yields are not as high as 2D NAND yields so that the number of good bits per wafer hasn’t reached the level the 3D bit density advantage would suggest.

Bit Cost

To calculate bit-cost we need wafer cost, bit density and yield. As we have seen above, wafer cost is heavily dependent on the specifics of the fab running the wafers. The bit density and yields also vary company to company. For example, Intel-Micron uses a CMOS-Under technique where some of the peripheral CMOS is formed under the memory array giving them higher bit density than their competitors. We also believe Intel-Micron have relatively good yields.

Intel-Micron started their initial 3D NAND production in their Fab 2 facility in Lehi Utah, is an older fab from 2007. Additional production was then added in part of fab 10N in Singapore, a fab that dates from 2011. It is only this year that we expect Intel-Micron to begin production in the greenfield 10X 3D NAND fab. Intel is also converting their Fab 68 in China to run 3D NAND. At their 2017 analysts meeting Micron showed the following graph, see figure 8.

Figure 8. 2D Versus 3D NAND Bit Cost.
Micron Technology 2017 Analysts Meeting.

From this graph we can see that Micron achieved a 30% bit cost reduction for 3D – 32-layer versus 2D – 16nm and expects a further 30% cost improvement for 3D – 64-layers. I believe this industry leading cost reduction is due to a mix of older fabs with partially depreciated assets, high bit density due to CMOS under the memory array and high yields.

Toshiba has recently said that 3D – 64-layers is a sweat spot and will finally be lower cost than 2D NAND. I believe this is a combination of un-depreciated fab resources and relatively lower yields at Toshiba.

Samsung has not made any public statement about cost but I believe they achieved cost cross over around 3D – 48-layers. I have heard they have very good yields.

String Stacking

As the number of layers in the memory stack increases, channel hole aspect ratios climb making the process more difficult and slower. At some point a change to string stacking is expected. In string stacking a set of layers is deposited and fully processed into memory cell and then one or more additional memory stacks are deposited and processed. String stacking adds masks and complexity but makes channel hole formation faster and easier.

At 64-layers it is known that Intel-Micron is using a 2-stack array and Samsung s not stacking. There is speculation that Toshiba will string stack but that is not confirmed as far as I am aware. It is believed that Samsung wants to avoid string stacking until at least 128-layers. Using the IC Knowledge – Strategic Cost Model I have compared a 2-stack approach to a single stack approach at 96 layers for a TCAT process in the same fab and found a 2-stack approach increases cost by approximately 14% so Samsung’s rumored preference for not stacking until 128-layers makes sense for their process.

As 3D NAND scales to 64-layers and beyond bit costs have been reduced below 2D NAND bit costs at all the major manufacturers. 3D bit production is now exceeding 2D bit production and with further scaling of layers 3D NAND should continue to scale and extend Moore’s law well into the next decade.

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