WP_Term Object
(
    [term_id] => 18
    [name] => Intel
    [slug] => intel
    [term_group] => 0
    [term_taxonomy_id] => 18
    [taxonomy] => category
    [description] => 
    [parent] => 158
    [count] => 342
    [filter] => raw
    [cat_ID] => 18
    [category_count] => 342
    [category_description] => 
    [cat_name] => Intel
    [category_nicename] => intel
    [category_parent] => 158
)

ASML ASyMptotic progress- When will we get to EUV?

ASML ASyMptotic progress- When will we get to EUV?
by Robert Maire on 02-24-2015 at 5:30 pm

  • ASML making progress – but is it fast enough?
  • ASML has missed 10nm , can it catch 7nm? An economic question
  • Day one at SPIE- Better tone than last year but still cautious

1000 simulated wafers versus 700 simulated
At the opening of the SPIE conference ASML announced that TSMC had reached 1000 wafers a day “exposed” (not printed or produced) by TSMC.

This is significant in two ways; though still just a simulation and not a real test of real wafer production it is a higher theoretical number than the test numbers “leaked” out by IBM over 6 months ago. The second and perhaps more important is that the test was run by a real contender in the semiconductor arms race, TSMC who last year embarrassed ASML at SPIE by announcing that the tool had shot itself in the foot. This would seem to imply that TSMC is more supportive which is also evidenced by their continued purchases of tools.

Is progress fast enough? Zeno’s paradox…

Though progress is clearly being made , we remain concerned that the amount of money and effort being put into EUV is producing fewer and smaller gains as we try to get closer to a “production” system. It would appear much like Zeno’s paradox or an asymptotic curve that incremental progress is slowing as we get closer to the goal.

The announcement of 90 watts of power is certainly better than the 75 watts previously discussed but it would have been a lot better to be talking about a doubling to 150 watts especially as we live in a binary world of Moore’s law.

Catching a moving Moore’s law train … That already left the 10nm station
The reason for our concern about progress rates is that the industry and Moore’s law is not waiting around for EUV to catch up. From discussions with a number of people at the show its clear that 10nm is long gone (as has been known by those in the industry) but the new question is how much, if any, of 7nm can ASML catch. Whereas there never seemed much very serious talk of ASML making 10nm (except by ASML) there is a lot of speculation about a 7nm intercept.

Economics enters the picture
Everything always comes down to the final arbiter of money. This year at SPIE there is clearly more talk about the cost of EUV versus multi-patterning. There was a good presentation of the cost of HiNA (high numerical aperture ) EUV versus multi-patterning.

We have suggested in the past that there should be an economic crossover point from multi-patterning where the EUV production decision becomes clear but it sounds as if that line is blurring a bit. Part of the reason is that the delay in EUV has caused other complications that may confuse the simple economic choice for EUV. One example is the need for multi-patterning in EUV anyway by the time it gets to HVM, thereby taking away one of the positive attributes . However its still hard to see how multi-patterning can win in the long run as we hear talk about quad and “oct” patterning as if they were viable alternatives forever.

It would be wrong to underestimate the semiconductor industry’s aversion to change…..and the industry has gotten very comfortable with multi-patterning.

No Breakthroughs or new news…

There does not appear to be any new news or break through moments so far at SPIE with ASML’s announcement being a ho hum confirmation of the slow pace rather than a positive surprise.

Alternatives not ready
DSA (directed self assembly) , NIL (nano imprint lithography) and direct write E beam lithography are still works in progress further behind than EUV but also not showered in money as EUV has been.

Canon appears to be furthest along with using NIL at Toshiba for NAND production and we wouldn’t be surprised to see it in limited use at some point. The talk of alternative technologies at the show has quieted as discontent with EUV has abated a bit.

Infrastructure not ready
The “ecosystem” for EUV is further behind than EUV itself and will clearly limit the introduction of EUV whenever it really becomes available. This is not new news as we have been talking about it for a long time and the problem has not changed nor have there been any changes in the significant participants, such as KLAC. This remains a major bottleneck for EUV’s progress to HVM.

No stock impact
As there isn’t anything incrementally positive to find at SPIE so far, we see no reason for any significant change in stock valuation. EUV remains a work in progress without a clear insertion point and alternatives have their issues as well.

We do continue to believe that both Lam and AMAT will have a long positive run in etch and dep to support multi-patterning which will clearly be around for quite a while.

Robert Maire
Semiconductor Advisors LLC


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