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High Level Synthesis Gets Stronger

High Level Synthesis Gets Stronger
by Daniel Payne on 02-24-2015 at 1:00 pm

High Level Synthesis (HLS) tools have been around for at least two decades now, and you may recall that about one year ago Cadence acquired Forte. The whole promise of HLS is to provide more design and verification productivity by raising the design abstraction from RTL code up to SystemC, C or C++ code. With any acquisition it is natural to ask a few questions, like:

  • Which EDA tool will live, and which will die?
  • What is the new product roadmap?
  • What happens to all of my legacy design work, will it be supported?

I spoke with David Pursley of Cadence on Monday to get an update on what they’ve been doing for the past 12 months in HLS. The really good news is that they’ve combined the best features of the Forte Cynthesizer tool with the Cadence C-to-Silicon Compiler tool, and named it Stratus HLS.

Related – Cadence Acquires Forte

This means that any customer already using Cynthesizer or C-to-Silicon Compiler can continue using their favorite HLS tool, or upgrade to the Stratus HLS tool to get the best of both tools. The Stratus HLS learning curve for existing users will be quite brief. The overall design flow stays the same where you can perform functional simulation with Incisive, formal analysis with JasperGold, HLS with Stratus, and logic synthesis with Encounter RTL Compiler:

Zooming in a bit into the HLS flow there is the familiar input languages (SystemC, C, C++) and RTL output:

Users of Stratus HLS manage the big picture items:

  • Function
  • Architecture
  • Constraints

Automation from Stratus then boosts productivity by managing:

  • Schedule of operations
  • FSM encoding
  • Area reduction
  • Timing
  • ECO
  • Clock gating
  • Pipeline registers
  • Consisten RTL style
  • Sharing datapath components

You can start to think about using this type of HLS on your next SoC design including both control and datapath logic, instead of constraining HLS to only DSP blocks. The interface IP and floating-point IP give you a re-use head start with synthesizable optimized SystemC building block.


Graphical analysis with links to source code

Blu Wireless Technology is an early user of Stratus HLS and they designed a multi-gigabit modem and have an early working prototype thanks to the automation provided even while the specifications were changing.

Related – White Paper about Blu Wireless

HLS has just become stronger as Cadence offers up the Stratus HLS tool as a combination of Forte Cynthesizer and Cadence C-to-Silicon Compiler tools. The HLS market continues to grow because users can measure their productivity improvements, QOR and benefits from high-level IP re-use.

Related – SystemC HLS Methodology


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