From Space-Central to Space-Time Balanced - A Perspective for Moore’s Law 2.0 and A Holistic Paradigm for EmergenceA friend of SemiWiki published an article on…Read More
The RISC-V and Open-Source Functional Verification ChallengeMost of the RISC-V action at the end…Read More
Sarcina Democratizes 2.5D Package Design with Bump Pitch Transformers2.5D package design is rapidly finding its stride…Read More
Addressing Reliability and Safety of Power Modules for Electric VehiclesAs electric vehicles (EVs) gain widespread adoption, safety,…Read More
Virtual platforms have been an area that has some powerful value propositions for both architectural analysis and for software development. But the fundamental weakness has been the modeling problem. People want fast and accurate models but this turns out to be a choice.
The first issue is that there is an unavoidable tradeoff… Read More
The IBM X-ForceTrend and Risk Report reveals how 2010 was a pivotal year for internet security as networks faced increasingly sophisticated attacks from malicious sources around the world. The X-Force reportedly monitors 13 billion real-time security events every day (150,000 events per second) and has seen an increase in … Read More
Stanley Kubrick’s 2001: A Space Odyssey showed us a world where machine vision allowed a computer to watch and interact with its human colleagues. Yet after 40 years of incredible progress in semiconductor design, the technology to make computer-based image and video analysis a reality is still not practical.
While working with… Read More
I can still remember the time, back in the mid-1980s, when I was at VLSI and we first discovered that we were going to have to worry about package pin inductance. Up until then we had been able to get away with a very simplistic model of the world since the clock rates weren’t high enough to need to worry about the package and PCB as… Read More
I will share with you some strategic information released by Cadence last week about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest… Read More
There have been some significant foundry announcements recently that if collated will give you a glimpse into the future of the semiconductor industry. So let me do that for you here.
First the candid EETimes article about TI dumping Samsung as a foundry:
Taiwan’s UMC will take the ”lead role’’ in making the OMAP 5 device on… Read More
Inroduction
In the early days we made paper plots of an IC layout then measured the width and length of interconnect segments with a ruler to add up all of the squares, then multiplied by the resistance per square. It was tedious, error prone and took way too much time, but we were rewarded with accurate parasitic values for our SPICE… Read More
The recent announcement from Tabula about the $108 million raised in its Series D round of funding is putting the focus on FPGA technology, and FPGA startups in particular. Who are these FPGA startups, what is their differentiation, where is the innovation, in the product or the business model?
When you say FPGA, you first think:… Read More
Samsung is the #1 electronics company, the #2 semiconductor company, and for 20+ years the world’s largest memory chip maker. Analysts expect Samsung to catch Intel by the year 2014. In the foundry business however Samsung is a distant #9 after more than a five year investment and here’s why:
Foundry 2010 Revenue:
(1) TSMC $13B
(2)… Read More
Intro
Earlier this month I drove to Mentor Graphics in Wilsonville, Oregon and spoke with Michael Buehler-Garcia, Director of Marketing and Nancy Nguyen, TME, both part of the Calibre Design to Silicon Division. I’m a big fan of correct-by-construction thinking in EDA tools and what they had to say immediately caught my… Read More
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