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Semiconductor Virtual Platform Models

Semiconductor Virtual Platform Models
by Paul McLellan on 04-19-2011 at 3:38 pm

Virtual platforms have been an area that has some powerful value propositions for both architectural analysis and for software development. But the fundamental weakness has been the modeling problem. People want fast and accurate models but this turns out to be a choice.

The first issue is that there is an unavoidable tradeoff between performance and accuracy; you have to give up one to get the other. But models that are fast enough for software development need to be millions of times faster than RTL and there is simply no way to get that sort of speedup automatically. Just as you cannot get from a Spice model to an RTL model by simply removing unnecessary detail, you can’t get from an RTL model to a virtual platform behavioral model by removing unnecessary detail.

Trying to create a model with both speed and accuracy seems to be the worst of both worlds. The model either has insufficient accuracy to be used for verifying the interaction of low-level software with the chip (in order to get higher performance) or else, if it has that accuracy, it will be too slow for software developers.

A better approach is to accept this and create both a high-speed model, for software development, and a medium-speed cycle-accurate model for hardware and firmware debug.

The medium-speed model can be created from the RTL automatically. Carbon Model Studio takes RTL models, completely accurate by definition, and delivers speedups of 10-100x by throwing away detail to produce a Carbonized cycle-accurate model. This guarantees the fidelity of the medium speed model to the actual chip.

Fast peripheral models, and in this context “peripheral” just means anything other than the processors themselves, are actually pretty simply to create in most circumstances. Often the peripherals have very simple behavior and the complexity in implementation comes from making them run fast in hardware: there’s close similarity between a 1 megabit Ethernet and a 1 gigabit Ethernet (or even 1 terabit) from a model point of view, for the implementation challenge not so much.

Of the solutions out there right now, this combination of a hand-crafted high-performance model (probably in SystemC) and an automatically generated medium-performance model that is guaranteed to match the RTL seems to be the closest that it is possible to get to the sweet spot. Like the old engineering joke about cheap-fast-good, pick any two. For virtual platform models it is fast-accurate pick one.

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