Automating Reset Domain Crossing (RDC) Verification with Advanced Data AnalyticsThe complexity of System-on-Chip (SoC) designs continues to…Read More
The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)Part 2 of this 4-part series reviews the…Read More
Collaboration Required to Maximize ASIC Chiplet ValueIt is a well-known fact that chiplets provide…Read More
One thing I do as an internationally recognized semiconductor blogger is listen to the quarterly conference calls of companies that drive our industry. TSMC is always interesting, I really like the honesty and vision of Dr. Morris Chang. Cadence is good, I always want to hear what Lip-Bu Tan has to say. Oracle and Larry Ellison, … Read More
At DVCon on Thursday March 1st (St David’s day for any Welsh readers) Jasper is sponsoring lunch from 12pm to 1.30pm. It will take place in the Cascade/Sierra ballrooms.
During lunch there will be a panel discussion Formal Verification from Users’ Perspectives with real users no how they mitigate risk in their designs… Read More
On my last graphics chip design at Intel the project manager asked me, “So, will this new chip work when silicon comes back?”
My response was, “Yes, however only the parts that we have been able to simulate.”
Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure… Read More
Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies… Read More
At DesignCon this week there was a panel on 3D standards organized by Si2. I also talked to Aveek Sarkar of Apache (a subsidiary of Ansys) who is one of the founding member companies of the Si2 Open3D Technical Advisory Board (TAB), along with Atrenta, Cadence, Fraunhofer Institute, Global Foundries, Intel, Invarian, Mentor, Qualcomm,… Read More
It has been a great conundrum to many of the 20[SUP]th[/SUP] century trained economists and Harvard’s Kennedy School of Government folks as to why a government led massive spending spree and Ben Bernanke’s non-stop printing presses can’t at least engender a mediocre economic recovery.
I blame 21st century Moore’s Law!
Today’s… Read More
Always in motion is the future. ~Yoda
For nearly ten years now, full-chip simulation engines have successfully used process models to perform OPC in production. New full-chip models were regularly introduced as patterning processes evolved to span immersion exposure, bilayer resists, phase shift masking, pixelated illumination… Read More
The ASIC business is getting more and more complicated. The ability to produce innovative die at a competitive price to solve increasingly complex problems just isn’t enough. The technology required to package that die is now front and center.
Here, at the junction of advanced design, process technology and state-of-the art … Read More
Next week there are two Apache, a subsidiary of Ansys, events. At DesignCon there are a couple of workshops on chip-package-system (CPS). In addition to Apache themselves, each of the two workshops has a number of representatives of leading edge companies doing semiconductor design. I already blogged about this in more detail… Read More
I have bloggedbefore Christmas about the Arteris-Sonics war, initiated by Sonics, claiming that Arteris NoC IP product was infringing Sonics patent. We had shown in this post that the architecture of Sonics interconnects IP product was not only older but also different from Arteris’ NoC architecture: the products launched … Read More
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