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SystemVerilog Assertions and Functional Coverage

SystemVerilog Assertions and Functional Coverage
by Daniel Payne on 09-24-2013 at 8:26 pm

Ashok Mehtahas designed processors at DEC and Intel, managed ASIC vendor relationships, verified networks SoCs, directed engineers at AMCC, and used SystemVerilog since it’s inception. He recently authored a book: SystemVerilog Assertions and Functional Coverage. The book is available in both hardcover and Kindle formats at Amazon.

Ashok Mehta, Senior Manager at TSMC

A couple of weeks ago Ashok contacted me and asked if I would review his book, so I asked for a Kindle version and then started reading it the next day. Amazon provides an easy way for you to send a Gift book to any Kindle user.

Right away I enjoyed his writing style because it came across like he was conducting a training class, engineer to engineer, not something theoretical, rather practical and hands-on. My learning style is by example, so this book was instantly attractive. The target audience for this book is both design and verification engineers, so maybe your team should read it in order to better communicate your expectations and start to use SystemVerilog to it’s fullest potential.

The book is divided into two parts:

  • Part I: SystemVerilog Assertions (SVA)

    • Introduction, history
    • Methodology
    • Immediate assertions
    • Concurrent assertions
    • Sampled value functions
    • Operators
    • System functions and tasks
    • Local variables
    • Recursive properties
    • Asynchronous assertions
    • IEEE 1800-2009 features
    • Labs
  • Part II: SystemVerilog Functional Coverage (FC)

    • Introduction, differences with code coverage
    • Details of covergroups, coverpoints and bins
    • Performance tradeoffs
    • Coverage options

I’ve taught Verilog classes before, but hadn’t ventured into assertions yet, so this book laid a good foundation for me.
An assertion is simply a check against the specification of your design that you want to make sure never violates. If the specs are violated, you want to see a failure.

Figures are used liberally and help convey each new concept quickly to the engineering mind:

A simple bus protocol design and its SVA property

You’ll learn how to write assertions by looking at several examples, learning each new feature of the language and how to apply it to any digital design, plus the benefits to both the design and verification engineers. There’s plenty of useful information on what to use when writing SVA and why, then what to avoid and why.

The language syntax is explained and then examples show how to put it into practice:

Clock Delay Range

Recall that ‘assert’ checks for failures in your design and ‘cover’ sees if the property did get exercised (i.e. got covered).

Here’s kind of the big picture on how the SystemVerilog language works with assertions and coverage:

Assertion based verification (ABV) and functional coverage (FC) based methodology.


If you are designing or verifying an SoC using SystemVerilog, then this book on SystemVerilog assertions and functional coverage can benefit your team by giving you best practices backed by an experienced user of the language. In the end your project will more likely work on first silicon if you adopt an assertion based verification methodology.

lang: en_US

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