See Autonomous Chip Design in Action with ChipAgents at DAC 2026Making the AI wave at DAC 2026 in…Read More
Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026Easy-Logic, a leading provider of high-performance Engineering Change…Read More
The Accidental Infrastructure: How Crypto Miners Built the Foundation of the AI BoomMost crypto forty-niners died broke in a warehouse…Read More
From Detection to Safety: Reframing Fault Simulation for Functional SafetyIn the early 1980s, when computer-aided engineering (CAE),…Read More
Driving the Future through the “Talent Empowering Program”: Why TSMC Charity Foundation’s Youth Career Initiative MattersThe future of work will not be shaped…Read More
Jim Feldhan, President of Semico Research presented earlier this month at the Impact Conference on the topic: Focus on the IP Ecosystem. I’ve reviewed his 19 page presentation, and summarize it with:
Donald Rumsfeld categorized what we knew into known unknowns and unknown unknowns. In a chip design, those unknown unknowns can bite you and leave you with a non-functional design, perhaps even intermittent failures which can be among the hardest problems to debug.
Chips are too big to do any sort of full gate-level simulation,… Read More
My very first thought when hearing about HSPICE is using it for IC simulation at the transistor-level, however it can also be used to simulate a package or PCB interconnect very accurately, like in the PCB layout of a DDR3 system where timing is critical. I attended a webinar this morning that was jointly presented by Zuken and Synopsys… Read More
As a full time financial writer/investor, I am always on the lookout for compelling risk/reward opportunities, particularly in small-cap tech. While the world of large-cap tech is generally well understood by the investment/analyst community, smaller cap names are usually under-followed and often misunderstood. One such… Read More
Next year’s DVCon attendees can expect to learn about both practical solutions to their pressing problems that can be applied today and also receive a preview of the technologies that will affect them in the near future. DVCON is March 3-6, 2014 @ the DoubleTree Hotel in San Jose.
KEYNOTE: An Executive View of Trends and Technologies… Read More
We agree now that FD-SOI technology is Faster, Cooler, Simpler. But can it also be a cheaper technology? Let start with an overview of the current estimation of the development cost for complex SoC on advanced technology nodes. The following data are extracted from International Business Strategies, Inc 2013 report. The first… Read More
SEMI’s World Fab Forecast report, published in November, predicts that fab equipment spending will decline about -9 percent (US$32.5 billion) in 2013 (including new, used and in-house manufactured equipment). Setting aside the used 300mm equipment Globalfoundries acquired from Promos at the beginning of 2013 (NT$20-30 … Read More
Analog IC designers are gradually adopting what digital IC designers have been doing for years, metric driven verification. When you talk with analog designers about their methodology and approach, you hear terms like artisan being used which implies mostly a manually-oriented methodology. Thanks to automation from EDA companies,… Read More
As power has become one of the most important criteria in semiconductor design today, I was wondering whether there is a standard set for the power verification for an overall chip. We do have formats evolved like CPF and UPF and there are tools available to check power and signal integrity (SI), however I don’t see a standard objective… Read More
It was on 26th April 1985 (at 3pm to be precise) that the very first ARM silicon sprang in to life – it was a 25K transistor design implemented in 3um technology with just 2 layers of metal.
However back then the “A” in ARM stood for Acorn – ARM the company had yet to be formed. Acorn sold computers to schools and so cost… Read More
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Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?