Donald Rumsfeld categorized what we knew into known unknowns and unknown unknowns. In a chip design, those unknown unknowns can bite you and leave you with a non-functional design, perhaps even intermittent failures which can be among the hardest problems to debug.
Chips are too big to do any sort of full gate-level simulation, and a more flexible approach to x-propagation and detection, using static timing analysis, RTL lint tools and various flavors of formal verification. There are two fundamental problems with analysis of unknowns: excessive pessimism and excessive optimism.
When an X signal is propagated, then the algorithm can choose to set the value to 0 or 1 based on some heuristics, which leads to excessive optimism since the signal may have the other value. But if the X signals are all propagated as unknowns then there is excessive pessimism and sometimes the whole design can degenerate into a mess of unknown signals. Furthermore, signal paths can recombine and in some circumstances whether the signal is 0 or 1 then the output is well defined but shows as a (false) error.
In some cases, static tools are able to handle all these issues satisfactorily, and when they can they tend to be preferable to simulation. But sometimes validating RTL synthesis and final timing verification for example, the potential for optimism in the ‘x’ semantics of RTL simulation remains an issue that must be resolved dynamically.
Most teams validate ‘x’ propagation in gate-level simulation, but gate simulations are time-consuming, tedious to debug and overly pessimistic with respect to ‘x’ on re-convergent paths, which can result in simulation failures that do not represent real bugs. Gate-level simulations also can only be performed later in the simulation cycle since one needs a gate-level netlist, meaning that this time-consuming methodology for resolving x-propagation issues often delays the critical path to tape out.
Low power designs have additional x-related issues. When blocks are powered down or voltages are scaled then outputs may go unknown as a result. Almost all designs use some of these low power techniques these days. In mobile they are necessary for extending battery life and in tethered systems it is often not thermally manageable to have the whole chip powered up at once.
Synopsys’s VCS simulator has added technology called Xprop which eliminates ‘x’ optimism at RTL to enable correlation with hardware design behavior. Xprop can be used to reduce and potentially eliminate gate-level simulations for ‘x’ validation.
There is a recent webinar presented by Rebecca Lipon and Bruce Greeene of Synopsys. The webinar covers:
- Review the pros and cons of existing methodologies for x-validation
- Explain how VCS Xprop eliminates ‘x’ optimism in advanced simulation flows (such as VCS-NLP)
- Demonstrate how to debug ‘x’-related issues identified by VCS-NLP and Xprop using Verdi Power-Aware Debug
Link for more details and to replay the webinare are here. 45 minutes + 15 minutes of questions.Share this post via: