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Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)

Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)
by glforte on 11-14-2012 at 2:15 pm

Until now, the integration and testing of IP blocks used in large SOCs has been a manual, time consuming design effort. A new standard called IEEE P1687 (or “IJTAG”) for IP plug-and-play integration is emerging to simplify these tasks. EDA tools are also emerging to support the new standard. Last week mentor announcedTessent IJTAG,… Read More


Adesto Acquisition of Atmel Serial Flash: Strange Bedfellows?

Adesto Acquisition of Atmel Serial Flash: Strange Bedfellows?
by Ed McKernan on 11-14-2012 at 1:00 pm

On October 1, Adesto Technologies announced that it had acquired Atmel’s DataFlash and Serial Flash business groups. At first sight, this seemed a rather counter intuitive move for one of the most aggressive (and visible) companies in the emerging memory field. The purchase raised many questions to those, not least the moderator… Read More


The logic of trusting FPGAs through DO-254

The logic of trusting FPGAs through DO-254
by Don Dingee on 11-13-2012 at 8:15 pm

Any doubters of the importance of FPGA technology to the defense/aerospace industry should consider this: each Airbus A380 has over 1000 Microsemi FPGAs on board. That is a staggering figure, especially considering the FAA doesn’t trust FPGAs, or the code that goes into them.… Read More


Jasper User Group Keynotes

Jasper User Group Keynotes
by Paul McLellan on 11-13-2012 at 1:31 pm

I attended the Jasper User Group this week, at least the keynotes, the first by Kathryn Kranen the CEO of Jasper and the second by Bob Bentley of Intel.

Kathryn went over some history, going back to when the company was started (under the name Tempus Fugit) back in August 2002 with a single product for protocol verification. Now, since… Read More


Analog FastSPICE AMS — Simple, Fast, nm-Accurate Mixed-Signal Verification

Analog FastSPICE AMS — Simple, Fast, nm-Accurate Mixed-Signal Verification
by Daniel Nenni on 11-12-2012 at 7:00 pm


Verification and AMS are top search terms on SemiWiki so clearly designers have a pressing need for fast and accurate verification of today’s mixed-signal SoCs that include massive digital blocks and precision analog/RF circuits. They need simulation performance to verify the mixed-signal functionality, and they need nanometer… Read More


Cadence sets the Global Standards in VIP for AMBA based SoC

Cadence sets the Global Standards in VIP for AMBA based SoC
by Eric Esteve on 11-12-2012 at 11:48 am

We have shown in Semiwiki how strong Cadence position was in Verification IP (VIP) in a previous post focusing on Interface standards like SuperSpeed USB or PCI Express. But IP based functions are used everywhere in a SoC, not only to interface with the external world, and need to be verified, as well, like for AMBA based functions.… Read More


Next Generation FPGA Prototyping

Next Generation FPGA Prototyping
by Paul McLellan on 11-12-2012 at 7:00 am

One technology that has quietly gone mainstream in semiconductor design is FPGA prototyping. That is, using an FPGA version of the design to run extensive verification. There are two approaches to doing this. The first way is simply to build an prototype board, buy some FPGAs from Xilinx or Altera and do everything yourself. The… Read More


Why are AMS designers turned off by Behavioral Modeling?

Why are AMS designers turned off by Behavioral Modeling?
by Ian Getreu on 11-11-2012 at 8:10 pm

Analog Mixed-Signal (AMS) behavioral models have not caught on with the AMS designer community. Why? I suspect a significant reason (but certainly not the only one) is the way they are presented.

First, what is AMS behavioral modeling?

I define it as “a set of user-defined equations that decribe the terminal behavior of a component”.… Read More


Static Timing Analysis for Memory Characterization

Static Timing Analysis for Memory Characterization
by Daniel Payne on 11-11-2012 at 6:18 pm

Modern SoC (System On Chip) designs contain a larger number of RAM (Random Access Memory) instances, so how do you know what the speed, timing and power are for any instance? There are a couple of approaches:
[LIST=1]

  • Trust the IP supplier to give you models that use polynomial equations to curve-fit the performance numbers based
  • Read More

    TSMC Financial Update Q4 2012!

    TSMC Financial Update Q4 2012!
    by Daniel Nenni on 11-11-2012 at 4:00 pm

    The weather in Taiwan last week was very nice, not too hot but certainly not cold. The same could be said for the TSM stock which broke $16 after the October financial report where TSMC reported a sales increase of 15% over September. Revenues for this year thus far increased 19% over last year so why isn’t TSM stock at $20 like I predicted… Read More