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This afternoon and evening I was at GSA’s entrepreneurship conference at the Computer History Museum. The first two panel sessions were essentially on getting money into companies to get them started (or growing them), and getting money out when you have built the business.
The first session was officially titled Fueling… Read More
Yesterday was Intel’s Q2 conference call. I think that there are some interesting little pieces of information. The financials were what analysts expected although they did take down their guidance for the rest of the year. But that is never the interesting point of Intel conference calls (they almost always hit guidance).… Read More
Recently Bill Dally, nVidia’s Chief Scientist & SVP of Research, and a professor of electrical engineering and computer science at Stanford University, has been out speaking quite a bit including a “short keynote” at the Design Automation Conference and a keynote at ISC 2013. The DAC audience is primarily EDA tool users and… Read More
Configurable System IP from a Tool Providerby Randy Smith on 07-18-2013 at 11:00 pmCategories: EDA
While I have previously blogged on Forte’s Cynthesizer Workbench’s Interface Generator, I want to take another look from a different perspective. Watching the tool and IP together in action through public videos provided by Forte it struck me as odd what I did not consider earlier, on what should have been obvious to me – Forte is… Read More
The opening keynote to this year’s Semicon West was by Ajit Manocha, the CEO of GlobalFoundries entitled Foundry-driven Innovation In the Mobility Era. It is no secret that mobile applications, especially smartphones and tablets, are the most significant semiconductor market today. It is not just large, it is disruptive.… Read More
There still seems to be a lot of confusion here so let me set the record straight. In regards to the Apple Ax SoC, the Apple iPhone 5s will have Samsung 28nm Silicon. Samsung 28nm is still ramping but Samsung can make enough wafers and eat the yield issues no problem. The Apple iPhone 6 in 2014 will have TSMC 20nm as I reported previously.… Read More
Oasys Bakes a PIEby Paul McLellan on 07-17-2013 at 3:01 pmCategories: EDA
One challenge in building a modern SoC is that you want to minimize power, performance and area (PPA) while still getting your chip to market on schedule. Realistically, you can’t actually minimize all of these at once since they are tradeoffs: speeding up a critical path often involves upsizing drivers to larger cells which… Read More
SemiWiki is absolutely the best place to start of course. You can read observations, opinions, and experiences on a wide variety of semiconductor related topics from semiconductor professionals around the world. You can also mingle with the 653,105+ people who visit SemiWiki in the comment sections and the forum. Registration… Read More
When looking at the time to design and verify an SoC we’ve known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.
A second trend is the amount of Analog content in… Read More
Novati is a semiconductor company that you probably haven’t heard of. It has its roots in Sematech back when Sematech was mainly in Austin rather than New York where it is today. The Sematech fab first became an independent company and then acquired by SVTC and operated under that name for 4 years. Finally, last the investors… Read More
The Data Crisis is Unfolding – Are We Ready?