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Yes, I will be going to IDF again this year, even though it is the same day as the Apple new product announcement. As a born again Apple Fan that is really saying something but Intel has done a great job of motivating the fabless semiconductor ecosystem and I thank them for that.
Unfortunately, noticeably missing from the IDF presentation… Read More
Still not convinced on the value of FPGA-based prototyping systems, or using older technology? I’ve been trying to find the story beyond just bigger, badder FPGAs in a box that you pour RTL into – and found some hints in a webinar on the Synopsys HAPS-70 from earlier this year.… Read More
Engaging with the semiconductor ecosystem is critical to surviving in the fast paced times we work in. Face to face interaction at all levels is key and semiconductor IP is a prime example. How do you ensure that your IP meets objective quality requirements before integration into your SoC, and that your SoC is ready for handoff to… Read More
Jim Hogan is having his annual Heart of Technology charity barbecue at his home in Santa Cruz. This year it is on Saturday August 31st and it’s a luau. It is from 2pm to 8pm at 2171 Sunny Acres Drive, Santa Cruz. Each adult requires a tax-deductible donation of $50 to FleaHab of Santa Cruz County (kids are free).
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IC designers have been creating with hierarchy for years to better manage large design sizes, however for the test world the concept of hierarchy and emerging standards is a bit newer. TSMC and Synopsys jointly created a webinarthat addresses hierarchical test, so I’ve attended it this week and summarized my findings here.… Read More
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There never seems to be enough time in a SoC project to simulate all of the cycles and tests that you want to run, so any technique to accelerate each run is welcomed. You can just wait for your software-based RTL simulator to finish running, or you can consider using a hardware-based accelerator approach. I learned more about one such… Read More
Timing exceptions are ways of guiding design tools, primarily synthesis and static timing analysis (STA), but these days also place & route and perhaps other tools. Most paths in a design go from one register to the next register. Both registers are on the same clock, and the design needs to ensure that the signal can make it from… Read More
[The VLC developed by Edison2, winner of the Progressive Automotive X-Prize]
Now that we have “The Very Light Car” of the world at more than 100 MPG!! Yes, this is the car developed by Edison2, one among the three winners of the Progressive Insurance Automotive X-Prize, a global competition; Edison2 won in the main stream class. … Read More
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Huawei’s and SMIC’s Requirement for 5nm Production: Improving Multipatterning Productivity