The Advance Semiconductor Manufacturing Conference was held on May 3[SUP]rd[/SUP] through May 6[SUP]th[/SUP] in Saratoga Springs, New York. ASMC brings a unique operational perspective to technical conferences related to semiconductors. In this blog I wanted to discuss what I thought was the most interesting paper of the conference, one of the keynotes given by Thomas Caulfield of Global Foundries entitled “Balancing Eco-System Value Creation and Value Capture”
But first I have to admit to a bit of a surprise here, I am generally not a fan of conference keynote addresses because I think they are often attempts to stake out some grand vision that they then fall short of. In this particular case, at least from my perspective there was enough really interesting information in the presentation to make it both interesting and informative.
Megatrends and connectivity
The keynote began with a review of some of the overreaching trends that are driving the semiconductor industry: expanding coverage and bandwidth needs for wireless connectivity, mobile computing and the internet of things driving low power solutions, network and storage backbones driving performance solutions and the need for security.
The evolution of computing was noted to have been driven from wired low bandwidth solutions to high bandwidth solutions leading to the internet of things.
The supply chain ecosystem is approximately $74 billion dollars of equipment and materials suppliers supporting approximately $419 billion dollars of semiconductors and related enterprises supporting approximately $1.55 trillion dollars of electronics.
Innovation benefits and costs
In the fourth installment of my recent series on Moore’s Law I argued that foundries have seen a pause in cost reduction around the 20nm/14nm nodes but that I expected this to be a temporary pause.
Moore’s Law is dead, long live Moore’s Law – part 4
Some other analysts have argued that 28nm is the low point for cost per transistor. In Dr. Caulfield’s slides he shows a pause in cost per transistor reduction at 20nm, he then shows that pause continuing at 14nm for other foundries but that at GlobalFoundries they see a “typical” cost per transistor reduction because of the high density of their 14nm process. Furthermore he is forecasting continued cost per transistor reductions at 10nm and 7nm in-line with our analysis.
GlobalFoundries view is that 28 nm will be a long lived node, 20nm will be a short lived node and 14nm will go on “forever”. 14nm offers “power, performance and cost” and many people are designing out of 28nm into 14nm skipping 20nm.
But there is a cost to these innovations, new materials and masks are rapidly piling up. For example there is a slide in the presentation showing approximately 40 masks at 65nm rising to approximately 57 masks at 28nm and approximately 68 masks at 16nm/14nm. This growth in process complexity drives up costs, reduces yields and increases cycle times. Dr. Caulfield noted that even at 1 day or 0.8 days per mask these processes take a long time to complete. The capital required for these processes are also increasing from around $65 million dollars per thousand wafers out at 65nm to around $100 million dollars for 28nm and around $135 million dollars at 16nm/14nm. The resulting improvements in transistor density are more than offsetting this so far, but the cost of entry is limiting the number of players at the leading edge (more on that below).
Design costs are also rapidly rising from approximately $60 million dollars at 65nm to around $140 million dollars at 28nm and nearly $500 million dollars at 16nm/14nm. Clearly only the highest running parts can provide a reasonable return on such a huge investment.
As noted above the cost of the latest state-of-the-art technologies is growing. At 14nm Dr. Caulfield noted that a $12 billion dollar investment is required to reach a competitive scale.
The rising costs of semiconductor facilities and technologies has driven consolidation to the point that there are now only four companies producing 14nm node logic processes, Global Foundries, Intel, Samsung and TSMC.
Global Foundries locations
With the IBM acquisition, GlobalFoundries now has three global manufacturing clusters, the Northeast tech corridor, Dresden and Singapore.
In the northeast tech corridor GlobalFoundries has the former IBM 200mm fab in Burlington Vermont running RF foundry, the former IBM 300mm fab in East Fishkill running ASICs and Server parts and the Global Foundries 300mm fab in Malta that is the R&D center and does 28nm and smaller manufacturing and is the only Global Foundries location running 14nm.
Dresden is a 300mm fab that originally came from AMD and is now focused on 20nm and larger manufacturing.
Singapore is the former Chartered fab location with 200mm and 300mm fabs. Singapore is the trailing edge manufacturing location for Global Foundries.
Dr. Caulfield offered the opinion that all the semiconductor manufacturing “corridors” that will be built around the world have been built.
During the question and answer session there was a question about labor cost differences around the world. Dr. Caulfield said that labor cost is a pretty small percentage of depreciating cost and he thinks you can innovate around it. Furthermore he said that materials and electric costs are pretty similar around the world. I would interject here that what is not the same around the world are tax policies and the availability of government incentives and these are a significant factor in the overall cost equation.
One of the big points of the presentation was collaboration and the 14nm collaboration between GlobalFoundries and Samsung is clearly a key part of GlobalFoundries strategy. GlobalFoundries has licensed Samsung’s 14nm process and customers will be able to get 14nm wafers on the same process from Global Foundries Fab 8 in Malta NY as well as Samsung’s S1 and S3 fabs in Giheung South Korea and S2 fab in Austin Texas.
Silicon On Insulator (SOI)
During the question and answer session I asked Dr. Caulfield about GlobalFoundries SOI plans. He replied that they are developing a 22nm process in Malta for manufacturing in Dresden. The goal is 14nm FinFET performance at 28nm costs. This would certainly be an interesting process if they can meet that goal. I do worry that GlobalFoundries appears to pursuing a lot of different directions for leading edge processes. IBM has a 14nm FinFET on SOI process with trench DRAM they will presumably have to support for server products, GlobalFoundries and Samsung have a 14nm FinFET on bulk process for general foundry use and GlobalFoundries is now developing a 22nm SOI process. That strikes me as a lot of leading edge processes for one company to support.
Dr. Caulfield sees logic technology continuing down to 3nm with consolidation and ultimately collaboration as key factors.