Every designer relies upon an underlying “compact” device model for circuit simulations – these models are the lifeblood of the IC industry. Designers may not be aware that there is an organization that qualifies models – the Compact Model Coalition – which operates under the umbrella of the Si2 Consortium: http://www.si2.org/cmc_index.php… Read More
Why IP Quality and Governance Are Essential in Modern Chip DesignBy Kamal Khan In today’s semiconductor industry, success…Read More
U.S. Electronics Production GrowingU.S. electronics production has been on an accelerating…Read More
Inference Acceleration from the Ground UpVSORA, a pioneering high-tech company, has engineered a…Read More
AI-Driven DRC Productivity Optimization: Revolutionizing Semiconductor DesignThe semiconductor industry is undergoing a transformative shift…Read More
Emulator-Like Simulation Acceleration on GPUs. Innovation in VerificationGPUs have been proposed before to accelerate logic…Read More
Secured SAM A5D4 MCU for Industrial, Fitness or IoT Display
The new SAMA5D4, ARM Cortex-A5-based, expands the SAMA5 microprocessors family, adding a 720p resolution hardware video decoder to target Human Machine Interface (HMI), control panel and IoT applications when high performance display capability are required. Cortex-A5 offers raw performance of 945 DMIPS (@ 600 MHz) completed… Read More
Nine Cost Considerations to Keep IP Relevant –Part2
In the first part of this article I wrote about four types of costs which must be considered when an IP goes through design differentiation, customization, characterization, and selection and evaluation for acquisition. In this part of the article, I will discuss about the other five types of costs which must be considered to enhance… Read More
Moore’s law limitations and gravitational collapse at lower process nodes
As stated in my previous article, about the complexity of the SOC with billions of transistors. It is essential to consider the real practical scenario for the two dimensional verses three dimensional structure of the chip. Although the new technological changes and evolution for the shrinking process node can create ease for… Read More
Solidly Across the Chasm
Last week I wrote about EDA companies crossing the chasm, with Jim Hogan (who needs no introduction) and Amit Gupta, CEO of Solido. So how did those rules work out for Solido?
See also Getting EDA Across the Chasm: 15 Rules Before and 5 After
The founding team of Solido:
- discovered process variation for analog was a problem as companies
What NoCs with virtual channels really do for SoCs
Most of us understand the basic concept of a virtual channel: mapping multiple channels of traffic, possibly of mixed priority, to a single physical link. Where priority varies, quality of service (QoS) settings can help ensure higher priority traffic flows unimpeded. SoC designers can capture the benefits of virtual channels… Read More
Something Old, Something New…EDA and Verification
When I got the opportunity to blog about verification, I thought, what new and interesting things should I talk about? Having started my EDA career in 1983, I often feel like one of the “oldies” in this business…remember when a hard drive required a static strap, held a whopping 33 MB, and was the size of a brick? Perhaps they should … Read More
Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes
There was a time when design goals were decided in the beginning, targeted on a particular technology node, design planning done for the same, and implementation done through point tools connected indesign flows customized according to the design. It’s no longer the case for modern SoC designs; there are multiple technology … Read More
TSMC Award Recognizes Andes’ IoT Credentials
The system-on-chip (SoC) movement is intrinsically linked to external IP products, and here, it’s not just fabless chipmakers who work closely with IP suppliers. Large foundries like TSMC also maintain close relationships with IP vendors to optimize their process nodes and libraries for processor cores and other design… Read More
What’s Testing Design Limits at ITC?
The 46[SUP]th[/SUP] IEEE International Test Conference (ITC) will be held the week of October 5, 2015 at the Disneyland Hotel Conference Center in Anaheim, California. ITC is where you will discover the latest ideas and learn about practical applications of test technologies.
As you take in panels, tutorials, presentations,… Read More
Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business