In a September 2026 World Economic Forum article, Ali El Kaafarani argues that energy companies should begin preparing their systems for post-quantum cryptography now. The reason is practical: power infrastructure lasts for decades, while replacing its security can take years. Equipment purchased today may still be operating… Read More
VSORA’s Sandra Rivera on the Inference Era: Demand Is Real, But Not Everyone SurvivesSandra Rivera, Chair of VSORA, joined Bloomberg’s The…Read More
Intel’s Open Software Blueprint: Why Production AI Needs More Than GPUsIntel’s strategic argument about enterprise AI is that…Read More
CTO Interview with Dr. Zakir Syed of ClockEdgeDr. Zakir Syed is Co-founder and Chief Technology…Read More
Overcoming the Edge AI Power Wall with Low-Voltage Foundation IPAs artificial intelligence (AI) workloads migrate to endpoint…Read More
Keysight Advances its Design Software with Agentic AIKeysight Technologies is opening a new route for…Read MoreTSMC OIP Ecosystem Forum 2026: Broadcom’s View of ASICs and Ecosystems
I spent a significant part of my career in the ASIC business. This segment of semiconductors has always been challenging, difficult and invigorating. There is something special about delivering a working custom chip that enables your customer to bring a world-changing product to market. It has always been a highly competitive… Read More
The Pivotal Moments That Gave Rise to Silicon Valley
The little-known decisions and breakthroughs—and the remarkable role of Robert Noyce—that helped shape the modern semiconductor industry
by Sunil Mehta
When people tell the story of how Silicon Valley came into being, they usually begin with a familiar sequence of events.
The transistor was invented at Bell Labs. William Shockley… Read More
SiFive and AMD Bring ROCm to RISC-V Datacenter Servers—and Why It Matters
SiFive and AMD demonstrated an AI workload that brings together two open technologies: the RISC-V processor architecture and AMD’s ROCm GPU software platform. At the AI Infra Summit on September 15, 2026, the companies showed ROCm 10.0 running on SiFive’s BigSky datacenter development server. SiFive P870-D CPUs served as the… Read More
Quantum Equivalence Checking. Innovation in Verification
Can quantum computing have any relevance to EDA? This month’s paper suggests it might have a role someday, in accelerating one of the most fundamental of EDA algorithms: SAT. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More
Why Advanced Chip Packaging Is Becoming a Design Problem
As chipmakers put more computing power into a single system, the challenge extends beyond making individual chips faster. They must connect multiple chips, memory stacks, power supplies, and sometimes optical components in a compact package. In the2026 TSMC OIP Forum talk “Addressing Inter-Die Complexity for 3D Multi-Die… Read More
Pollen Metrology: From a Decade-Long Bet to a Proven AI Platform for Semiconductor Manufacturing
Recently, I had the opportunity to speak with Johann Foucher, founder and CEO of Pollen Metrology, a French company whose journey offers a rare vantage point on how artificial intelligence is reshaping semiconductor manufacturing from the inside out. What makes Pollen Metrology’s story compelling isn’t just … Read More
Managing Power, Performance and Reliability in the Chiplet Era
Next-gen AI accelerators, high-performance processors, and complex computing architectures depend heavily on advanced packaging. Bringing multiple dies, chiplets, high-bandwidth memory, and advanced interconnects together into a single 2.5D or 3D package yields massive performance gains. However, this design evolution… Read More
Siemens and TSMC push AI deeper into chip design
Siemens and TSMC are expanding their collaboration on semiconductor design tools, with a focus on AI assisted workflows, advanced chip packaging and support for newer manufacturing processes. Their announcement centers on an AI agent intended to find and fix design rule violations: errors that can prevent a chip layout from… Read More
Agentic AI Can Reach GDS. What Must It Prove Before Engineers Trust It for Tapeout?
Agentic AI is beginning to move semiconductor engineering beyond copilots and isolated task automation.
From Agentrys’ public material and recent discussion, its architecture points toward a broader engineering flow:
Specification → RTL → verification → synthesis / physical design → PPA optimization → physical verification… Read More


The silent killer of analog reliability: Why SPICE misses floating net