SiFive and AMD Bring ROCm to RISC-V Datacenter Servers—and Why It Matters

SiFive and AMD demonstrated an AI workload that brings together two open technologies: the RISC-V processor architecture and AMD’s ROCm GPU software platform. At the AI Infra Summit on September 15, 2026, the companies showed ROCm 10.0 running on SiFive’s BigSky datacenter development server. SiFive P870-D CPUs served as the host processors, while AMD Radeon AI PRO R9700 GPUs handled AI inference for a Gemma4-E2B language model. The companies say they will continue evaluating how to optimize ROCm on RISC-V servers.

The division of work is central to the announcement. In an AI server, CPUs manage tasks such as running the operating system, coordinating applications, and preparing work for accelerators. GPUs perform the intensive calculations behind model training or inference. Software connects the two. ROCm supplies tools, libraries, and runtimes that let applications use AMD GPUs; RISC-V defines the instructions understood by the host CPU. The demonstration shows these pieces working together in a specific system. It does not establish that every ROCm workload is ready for every RISC-V server.

That distinction matters because bringing a new CPU architecture into a datacenter takes more than building a fast chip. Developers need operating systems, compilers, drivers, frameworks, and hardware interfaces that work together reliably. AI adds another layer: software must move data and commands between the host and the GPU without creating bottlenecks. If a platform cannot run the tools developers already use, its potential hardware advantages may never reach customers.

SiFive built BigSky to help tackle that practical work. The rackable development server is intended for software porting, workload tuning, and validation. Its published configuration includes 32 P870-D cores, 256 GB of DDR5 memory, and PCIe Gen5 connections for expansion devices. These specifications make it a place where developers can test a complete server setup and find problems that would be difficult to uncover from CPU designs alone. SiFive says BigSky systems are being produced in limited quantities for development.

Why does the AMD collaboration matter?

First, it gives RISC-V a more concrete path into accelerated AI computing. RISC-V has long offered organizations a standard instruction set on which to design processors, but datacenter buyers also need a working software ecosystem. Running an AMD GPU workload with a RISC-V host is evidence of progress on that ecosystem. Developers can now investigate the real engineering questions: which workloads run, where performance is lost, and what changes will make the combination useful at scale.

Second, it may eventually give server designers more choice. A company building AI infrastructure could evaluate different host CPU designs alongside AMD accelerators, choosing a combination that suits its workloads. RISC-V’s open standard also allows chip designers to tailor processors while keeping a common architectural foundation. That flexibility could be valuable when datacenters are trying to balance performance, power use, and cost. These are potential benefits, however; the demonstration provides no comparative performance or cost results.

Third, the collaboration gives AMD’s software ecosystem another possible host platform. GPU capability depends heavily on whether developers can bring existing models and applications onto a system. Extending ROCm to RISC-V could broaden the range of servers on which AMD GPU workloads can be explored. For customers planning infrastructure years ahead, that possibility may be as interesting as the immediate demo: it suggests a route to more combinations of CPUs, GPUs, and server designs.

The companies have framed the project as ongoing optimization. Their stated aims include faster processing, more acceleration use cases, and support for larger models. Those goals identify what remains to be proved. A small language model running in a demonstration-only system is an encouraging milestone, but production deployment would require broader application support, repeatable performance measurements, and evidence of reliability under sustained workloads.

Bottom Line: It is practical as much as symbolic. SiFive and AMD have shown that an open-standard RISC-V host can participate in a ROCm-powered AI system. The next measure of success will be whether developers can turn that working example into an efficient, dependable option for real datacenter workloads.

Contact SiFive

Also Read:

RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026

The Sky’s the Limit: SiFive’s BigSky Brings RISC-V to the Datacenter

SiFive’s P570 Gen 3 Pushes RISC-V Further Into the AI Era