RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026

RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. Its defining technical characteristic is not merely openness, but disciplined modularity. Four ratified base ISAs—RV32I, RV64I, RV32E, and RV64E—establish complete unprivileged programming models, varying address width and integer-register count. Extensions then add reusable capabilities such as multiplication, atomics, floating point, compressed instructions, vectors, and virtualization. This factoring allows implementers to specialize processors without redefining common semantics or rebuilding the software ecosystem.

That flexibility is bounded by an explicit encoding policy. RISC-V International defines standard and reserved spaces, while permanently allocating custom space for vendor features. A vendor instruction is therefore legitimate when placed in custom encoding space and identified conventionally, but becomes non-conforming if it occupies standard or reserved space. The distinction separates architectural diversity—different processors solving different problems—from fragmentation, in which equivalent functions are implemented incompatibly.

The architecture describes harts, or hardware threads, within execution environments rather than prescribing particular microarchitectures. An execution environment controls initial state, memory properties, I/O, interrupts, exceptions, and environment calls; the Linux user ABI is one example. Privilege is similarly layered. User, supervisor, machine, virtual-user, and virtual-supervisor modes remain cleanly separated, while the hypervisor extension supplies two-stage address translation. Because specifications do not assume higher privilege levels exist, privileged functions can be trapped and emulated without architectural virtualization holes.

Vector processing illustrates RISC-V’s scalability. The ratified RVV extension supplies 32 vector registers with implementation-selected VLEN, ranging in cited implementations from 32 to 16,384 bits. Vector-length-agnostic software discovers the available length dynamically, so one binary can exploit narrow embedded datapaths or wide accelerator datapaths without recompilation. LMUL groups registers to support mixed-width computation and reduce instruction demand. Proposed matrix approaches extend this model through vector dot products, matrix functional units, matrix engines, or combined matrix/vector engines.

Profiles convert modularity into dependable software targets. RVA application-processor profiles specify a base plus mandatory extensions and curated options, giving operating systems and binary distributions a predictable feature floor. RVA23, ratified in October 2024, makes vector and hypervisor support mandatory and defines high-performance vector cryptography as a localized option. Development options preview likely future mandates; expansion options cover costly, discoverable facilities such as matrix engines; transitory options may disappear; and localized options accommodate jurisdictional requirements. Minor releases add options without new mandates, preserving compatibility within a major generation.

Standards above the ISA complete the platform. The RISC-V server specification combines RVA23 processors with Advanced Interrupt Architecture support, PCIe and IOMMU, UEFI and ACPI, TPMs, UARTs, and established BMC management protocols. A planned RVM profile and subsystem apply similar discipline to richer microcontrollers, including fast interrupts, nested physical-memory protection, security, debug, and trace. Security mechanisms already include PMP, supervisor domains, IOMMU integration, cryptography, data-independent timing, control-flow integrity, pointer masking, and RISC-V Worlds, which tags bus transactions so multiple mutually distrustful compartments can be isolated.

The presentation also addresses performance misconceptions. Variable-length instructions encode their size in two bits, simplify decoding relative to x86, and improve code density or encoding expressiveness. RISC-V combines comparison and branching, so implementations do not inherently depend on instruction fusion, although fusion remains optional. New optimization-guidance options further align software with microarchitecture: Oilsm tells compilers to prefer hardware handling of misaligned scalar and vector accesses, while Ovlt indicates that vector execution should optimize around the dynamic vl value rather than reduced LMUL choices.

Why it Matters: The result is an architecture designed to scale through coordination rather than ownership. Roughly 200 RISC-V extensions may appear complex, but profiles prevent general-purpose software from targeting arbitrary combinations, while reusable extensions reduce duplicated architecture work. Customization remains available where differentiation matters; standardized profiles and platforms constrain it where binary compatibility matters. This balance positions RISC-V not as an open-source processor implementation, but as an open ISA and platform framework capable of supporting both highly specialized hardware and broad, durable software ecosystems.