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On May 15th TSMC “announced its intention to build and operate an advanced semiconductor fab in the United States with the mutual understanding and commitment to support from the U.S. federal government and the State of Arizona.”
The fab will run TSMC’s 5nm technology and have a capacity of 20,000 wafers per month (wpm). Construction… Read More
Mutation testing is an intriguing idea, but is it useful? Paul Cunningham (GM of Verification at Cadence), Jim Hogan and I continue our series on novel research ideas, here looking at a paper examining the pros and cons of this topic. Feel free to comment if you agree or disagree.
The Innovation
This month’s pick is Which Software … Read More
Hours after agreeing to build a fab in US TSMC will stop selling to Huawei- Repercussions will reverberate through all tech: Semis, semi equip, chip customers, all collateral damage.
It has been reported by Nikkei and other sources that TSMC has stopped taking orders from Huawei in order to comply with US export controls.
The road to a truly usable design management solution for electronic design has been a long and twisty one. Initially just handling EDA tool data was a struggle, let alone addressing mutli-user and multi-site needs. Of course, all along every EDA tool development company was internally using software revision control, which … Read More
Cybersecurity in 2020 will be evolutionary but not revolutionary. Although there is always change and churn, much of the foundational drivers remain relatively stable. Attacks in the next 12 months are likely to persist in ways already known but taking it up-a-notch and that will lead to a steady escalation between attackers… Read More
With Tesla Motors’ CEO Elon Musk spewing accusations of civil rights violations and fascism in the face of restrictions forcing him to keep his Fremont, California factory closed it is tempting to assume that Tesla is suffering through the shutdown with the rest of us. Don’t kid yourself. The COVID-19 pandemic is a crisis tailor-made
Tom Fitzpatrick, a Strategic Verification Architect at Mentor, a Siemens Business, has worked on IEEE and Accellera standards like Verilog 1364, System Verilog 1800, UVM 1800.2 and is Vice Chair of the Portable Stimulus working group, so when I heard that he was doing a webinar on how PSS can be used to create better stimulus for … Read More
The foundation of SemiWiki.com has always been to transition live semiconductor related events to an easy to digest digital format via a worldwide online semiconductor community. SemiWiki is staffed by working semiconductor professionals that transform live events, press releases, whitepapers, webinars and other collateral… Read More
Over the years SerDes (serializer/deserializer) based connections have proliferated into just about every connection within and among computing systems. Years ago, parallel interfaces were the most common method of moving data, but issues of signal integrity, synchronization and power simply became too much for the required… Read More
Design complexities in reset, like everything else in big SoC designs, has become incredibly complex, for all sorts of reasons. Long, long ago reset was something you just did once, when you turned the power on. Turn on, then hold reset for some amount of time until everything is in a known starting state, and off you go. Nice and simple.… Read More
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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival