Investors of capital, whether financial or human, utilize numerous methods to decide to participate with an early-stage / seed-stage technology company. The risks are, by definition, much higher than later stage companies pursuing investment in their Series B/C or beyond rounds. It is helpful to establish consistent “health… Read More
Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V ExtensionThe rapid growth of signal processing workloads in…Read More
2026 Outlook with Richard Hegberg of Caspia TechnologiesTell us a little bit about yourself and…Read More
Siemens EDA Illuminates the Complexity of PCB DesignAs heterogeneous multi-die design becomes more prevalent, the…Read More
Accelerating Advanced FPGA-Based SoC Prototyping With S2CHaving spent a significant amount of my career…Read More
Verification Futures with Bronco AI Agents for DV DebugVerification has become the dominant bottleneck in modern…Read MoreCooley’s 11 Quickie Questions About Virtual DAC’20 Last Week!
Just a little funny history, after I started my Silicon Valley Blog in 2009 several EDA CEOs bullied me into creating my own site to compete with John Cooley’s DeepChip.com. Competition is good, right? One good friend and CEO even suggested I call it DeepNenni.com. Thankfully we came up with something a little less awkward,
LRCX Strong Beat and Guide
Lam reported strong beat & guide, memory returns-
China trade and Covid impact near zero-
Looking at a strong H2 with WFE in mid $50B+-
Back on Cruise Control
Lam reported a great quarter, easily beating expectations coming in at $2.79B and $4.78 in non GAAP EPS-
Guide is for $3.1B +-$200M and EPS of $5.06+-$0.40-
Margins and all… Read More
Synopsys Presents SAT-Sweeping Enhancements for Logic Synthesis
There was a “research reviewed” panel on Thursday at DAC entitled Shortening the Wires Between High-Level Synthesis and Logic Synthesis. Chaired by Alric Althoff of Tortuga Logic, the panel explored methods to deal with wire delays in high-level synthesis and logic synthesis. The four speakers and their focus were:
- Licheng
CEO Interview: Ljubisa Bajic of Tenstorrent
Ljubisa Bajic is the CEO of Tenstorrent, a company he co-founded in 2016 to bring to market, full-stack AI compute solutions with a compelling new approach to address the exponentially growing complexity of AI models.
What is Tenstorrent?
Tenstorrent is a next-generation computing company that is bringing to market the first… Read More
DAC Panel – Artificial Intelligence Comes to CAD: Where’s the Data?
Artificial Intelligence (AI) and Machine Learning (ML) are becoming more and more commonplace in our world. We have Siri, Alexa and Google Assistant that understand our voice commands. Vision systems that recognize objects are used for facial recognition, autonomous driving, medical, geographical and many other applications.… Read More
Imec Technology Forum and ASML
On Thursday July 9 Imec held a virtual technology forum. Imec is one of the premier research organizations working on semiconductor technology and their forums are always interesting. My area of interest is process technology and the following are my observation in that area from the forum.
Luc Van Den Hove
Luc Van Den Hove is the… Read More
Designing AI Accelerators with Innovative FinFET and FD-SOI Solutions
I had the pleasure of spending time with Hiren Majmudar in preparation for the upcoming AI Accelerators webinar. As far as webinars go this will be one of the better ones we have done. Hiren has deep experience in both semiconductors and EDA during his lengthy career at Intel and now with a pure play foundry. He is intelligent, personable,… Read More
DAC Panel: Cadence Weighs in on AI for EDA, What Applications, Where’s the Data?
DAC was full of great panels, research papers and chip design stories this year, the same as other years. Being a virtual show, there were some differences of course. I’ve heard attendance was way up, allowing a lot more folks to experience the technical program. This is likely to be true for a virtual event. I’m sure we’ll see more… Read More
#57DAC – Panel Discussion of High Level Synthesis
Presenters took a trip down memory lane at DAC this year by having a panel discussion on HLS (High Level Synthesis) spanning from 1974 to 2020, and that time period aligns with when I first graduated from the University of Minnesota in 1978, starting chip design at Intel, then later transitioning into EDA companies by 1986. Marilyn… Read More


AI Bubble?