Architecting Your Next SoC: Join the Live Discussion on Tradeoffs, IP, and Ecosystem RealitiesDesigning a system-on-chip (SoC) has never been more…Read More
CEO Interview with Andrew Skafel of Edgewater WirelessAs the demand for high-capacity, low-latency wireless networks…Read More
CAST Webinar About Supercharging Your Systems with Lossless Data Compression IPsMuch of advanced technology is data-driven. From the…Read More
cHBM for AI: Capabilities, Challenges, and OpportunitiesAI’s exponential growth is transforming semiconductor design—and memory…Read More
Prompt Engineering for Security: Innovation in VerificationWe have a shortage of reference designs to…Read More
I recall an early custom IC designed at Wang Labs in the 1980s without any DFT logic like scan chains, then I was confronted by Prabhu Goel about the merits of DFT, and so my journey on DFT began in earnest. I learned about ATPG at Silicon Compilers and Viewlogic, then observability at CrossCheck where I met Jennifer Scher, now she’s… Read More
The semiconductor industry continues to drive innovation and constantly seeks methods to lower costs and improve performance. The advantages of custom I/O libraries versus free libraries can be seen as cost-savings or, more importantly, new markets, new customers, and new business
opportunities.
At DAC 2023, Certus Semiconductor… Read More
Semiconductor capital expenditures (CapEx) increased 35% in 2021 and 15% in 2022, according to IC Insights. Our projection at Semiconductor Intelligence is a 14% decline in CapEx in 2023, based primarily on company statements. The biggest cuts will be made by the memory companies, with a 19% drop. CapEx will drop 50% at SK Hynix… Read More
Constrained random methods in simulation are universally popular, still can the method be improved? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More
The relentless advancement of mobile phone technology continues to push boundaries, demanding SoCs that deliver ever-increasing performance while preserving extensive battery life. To meet these demands, the industry is progressively embracing lower technology nodes with current designs being taped-out at 5nm or below.… Read More
On the heels of the TSMC Symposium and the Intel Foundry update, Samsung held their Foundry Forum today live in Silicon Valley. As usual it was a well attended event with hundreds of people and dozens of ecosystem partners. The theme was the AI Era which is appropriate. As I have mentioned before, AI will touch most every chip and there… Read More
Keysight EDA will have a large presence at this year’s DAC in San Francisco July 9-13. For a better understanding of what’s happening with Keysight EDA at DAC I talked to my contacts to learn that they have three main messages this year:
You may recall that Keysight acquired Cliosoft… Read More
The transformation of the vertically integrated electronics value chain to a disaggregated supply chain has brought tremendous value to the electronics industry and benefits to the consumers. This transformation has driven the various players to become highly specialized in order to support the market trends and demands … Read More
At the 2023 SPIE Advanced Lithography and Patterning conference, ASML presented an update on its EUV lithography systems in the field [1]. The EUV wafer exposure output was presented and is shown below in table form:
From this information, we can attempt to extract and assess the EUV wafer output per quarter. First, since there … Read More
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Musk’s new job as Samsung Fab Manager – Can he disrupt chip making? Intel outside