Synopsys Advances Hardware Assisted Verification for the AI EraAt the 2026 Synopsys Converge Event, Synopsys announced…Read More
Chemical Origins of Environmental Modifications to MOR Lithographic ChemistryIn the pursuit of advanced extreme ultraviolet (EUV)…Read More
Post-Silicon Validating an MMU. Innovation in VerificationSome post-silicon bugs are unavoidable, but we’re getting…Read More
Securing UALink in AI clusters with UALinkSec-compliant IPA classic networking problem is securing connections with…Read More
GTC 2026: Agentic AI for Semiconductor Design and Manufacturing Janhavi Giri, PhD Principal…Read More
Intro
Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.
Notes
Why do this?
– Reduce leakage
– Increase gate lengths on paths with slack
–… Read More
Intro
I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.
Notes
Proplus – US company, founded in 1995 (Used to be Celestry, acquired… Read More
Intro
Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.
Daniel Borgraeve (on right)
Notes
Edxact
– Started seven years ago… Read More
Intro
Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.
Notes
New in 2011
– New GUI with schematic, layout and constraints
o Cross probing between all three windows
– Schematic for constraint entry
o Can start with a blank… Read More
Intro
My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.
Notes
Interconnect Modeling- Open Source Interconnect Technology Format (ITF)o Used by Star RC
–… Read More
Intro
Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.
Karen Mangum
Notes
I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.
Max-3D – Can handle stacked wafers with TSV
– Gary Smith’s list of must-see for 3D
–… Read More
Intro
Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).
Notes
Quarterly release: 2011 Q2 now
Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools
Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.
Device Noise – three … Read More
GLOBALFOUNDRIES showed off its 28nm design ecosystem at #48DAC last week in San Diego. The company featured a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership… Read More
Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.
Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The… Read More
Intro
Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.
Notes
GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.… Read More
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