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SystemVerilog 2012 at DAC

SystemVerilog 2012 at DAC
by Daniel Payne on 05-29-2012 at 3:59 pm

I first met Stuart at Mentor Graphics back in 1995 or so, and he is one of the most knowledgable persons around for all things Verilog.

Stuart Sutherland is the editor for the IEEE 1800 SystemVerilog standard, so if you’re attending DAC and care about SystemVerilog then consider attending the Birds of a Feather meeting held 7 to 8 PM Tuesday evening, room 306.

There will be a presentation summarizing the many significant new features that have been added to SystemVerilog, followed by informal discussion on the importance and proper application of these new features in design and verification projects. The presentation will be by Stuart Sutherland, editor of the IEEE 1800 SystemVerilog standard, and expert trainer of using SystemVerilog. Please invite any SystemVerilog users or tool developers who will be at DAC to attend this session. The DAC link for this meeting is: http://www.dac.com/additional+meetings.aspx?event=355&topic=5

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