Intel 10nm process problems -- my thoughts on this subject

[Daniel Nenni]

Actually... read the article and it will show you the math. Personally, I see SemiAccurate as an opinion piece, but a fact-inspired one <g class="gr_ gr_31 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del multiReplace" id="31" data-gr-id="31">non</g>e the less. Afaik they called the 10nm delay before even Intel management thought it would be required.

Fact inspired..... good one. I don't particularly care for Charlie. I read his site when I first started blogging and found him to be wrong as much as right, especially when it comes to the foundries. I did meet him onetime and found him to be an okay guy except that he spends a lot of time looking at his feet when talking.

The financial side is not my area of expertise but I do know people who are much more qualified than Charlie. Scott Jones for example. I would call Scott fact based versus fact inspired though.

 

[raghu78]

Hahahaha... What does that actually mean? Show us the math? Fake news.

Daniel if a process which was planned to go to HVM in 2016 fails to go into HVM till 2020 we have to seriously question its viability. Intel seems to be introducing Cooper Lake SP on 14++ as a follow up to Cascade Lake SP. That should give you an idea of how much Intel thinks 10+ will help their most important DCG product roadmap in 2020. When Intel cannot even say with confidence that ICL SP will ship in H1 2020 you have to question if Intel's process will be viable and more importantly will it be competitive with the rest of the industry. TSMC N5 is expected to be in HVM in 2020 and TSMC N3 is planned for HVM in 2022. If Intel cannot get 10+ based server products out in 2020 I have to agree that it will not be viable at a financial level and Intel is better off taking a decision soon whether they can get their 7nm out in HVM in 2022 or would they want to go fabless and plan their product roadmap with TSMC.

Actually... read the article and it will show you the math. Personally, I see SemiAccurate as an opinion piece, but a fact-inspired one <g class="gr_ gr_31 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del multiReplace" id="31" data-gr-id="31">non</g>e the less. Afaik they called the 10nm delay before even Intel management thought it would be required.

Yeah charlie really nailed the Intel 10nm debacle long before anyone had a clue. I think Daniel was the other who said that Intel could skip 10nm and go to 7nm back in 2015.

 

[raghu78]

Scotten, thanks for commenting here.

Regarding this note, 36nm vs 40nm is not the same as SADP vs SAQP. E.g. Intel went SADP on 45nm node, so for them 40nm-36nm transition would have been nothing more than 10% reduction with no changes in patterning technique.

Are you confused ? SADP limit is 40nm and thats exactly the minimum metal pitch (MMP) chosen by TSMC and GF. Samsung went with EUV for metal and has a 36nm MMP. Intel is the only foundry who went below 40nm for metal and were forced to use SAQP immersion litho for metal.

 

[Daniel Nenni]

Daniel if a process which was planned to go to HVM in 2016 fails to go into HVM till 2020 we have to seriously question its viability. Intel seems to be introducing Cooper Lake SP on 14++ as a follow up to Cascade Lake SP. That should give you an idea of how much Intel thinks 10+ will help their most important DCG product roadmap in 2020. When Intel cannot even say with confidence that ICL SP will ship in H1 2020 you have to question if Intel's process will be viable and more importantly will it be competitive with the rest of the industry. TSMC N5 is expected to be in HVM in 2020 and TSMC N3 is planned for HVM in 2022. If Intel cannot get 10+ based server products out in 2020 I have to agree that it will not be viable at a financial level and Intel is better off taking a decision soon whether they can get their 7nm out in HVM in 2022 or would they want to go fabless and plan their product roadmap with TSMC.

Yeah charlie really nailed the Intel 10nm debacle long before anyone had a clue. I think Daniel was the other who said that Intel could skip 10nm and go to 7nm back in 2015.

The thing is, predicting that a process will be late is not a big deal because most of them are. We put our best foot forward and hope for a smooth ramp but rarely is that the case. Which is why TSMC does the half nodes that share the same fabs (20nm/16nm, 10nm/7nm).

I did say skip 10 and jump to 7 and GF did just that. TSMC could not because of Apple and the process learning that is required.

So, if you want to look at a spreadsheet and say that Intel 10nm is not as financially viable as 14nm or 22nm that is fine. But had it not been for 10nm I do not think Intel could jump to 7nm unless they followed the same conservative path as TSMC, which GF did. You also have to realize that Intel 7nm requires full EUV and that is not ready yet so "jumping" to 7nm would have broken both legs, my opinion.

By the way, I was the one that outed the Intel 14nm yield problems. For Intel 10nm I knew when the process moved to Israel but I do not know why it has not been released yet. As with 14nm, Intel will come clean at some point in time so it will be interesting to see what the real story is. Until then it is conjecture, which is entertaining, but it is conjecture.

 

[count]

I don't think skipping to 7nm is an option for Intel either. Intel 7nm is expected to be a completely new gate type, maybe nanowire. So trying to figure that out at the same time as EUV when issues around SAQP and cobalt aren't fully resolved? Also from an economic standpoint, without reuse from 10nm, is 7nm even going to be viable?

Probably by the end of this year, before or shortly after a new CEO comes in, we will get more information. Noone is going to step into a job where they are going to be forced to take the blame for this boondoggle or for not communicating it. What will likely happen is the quarter before a new CEO starts, or the quarter after, Intel is going to kitchen sink it. In Q2, look for hints in guidance around problems in Q3, and then in Q3 look for a ton of one time costs and write downs. Then a new CEO can step in and after 2-3 years can point to a track record of increased profits (from a kitchensinked Q3) and claim a successful turnaround.

 

[IanD]

Do you realize that transistors are not the only source of losses, they do occur in the IC as well? So what happens when your thermal resistance between the source of losses and the cooler which dissipates most of them is 4x higher?

I actually do have very high respect for people sharing first-hand experience, but let me ask you: did you do actual measurements of die and IC temperatures -- all-copper IC vs CuCo stack? Did you run at least any simulations?

Because in case you didn't or miss that IC itself is a source of heat that must be dissipated, you're simply not in position to make such comments. Over at RWT some people had good fun at my findings, including the gasket effect, but as clues started coming in, the laughs died away, and none of those who had a good laugh are even seen anymore commenting on my posts.

By calling it "thermal gasket effect" I simply follow established tradition (skin effect, Miller effect, etc.). Naming it after myself is just too arrogant, but of course my ego would be very much pleased if the effect of using metal with low thermal conductivity in metallization stack on temperature fields in an IC gets named after the person who described it first.

Take it from me, if I had what it takes to do actual measurements to back my findings, I would have done so. Unfortunately I don't.

Having been involved in high-end ASIC design for far too many years, I've done extensive thermal simulations of real devices using Cu BEOL, including all thermal resistances on the die, in the package, TIM1, heatspreader, TIM2, heatsink and PCB and so on, and in every case (for flip-chips with heatsinks, which is what we're talking about) the amount of heat dissipated up through the Cu BEOL through the package substrate/balls/socket (if used) and into the PCB (remember the die is upside down) is negligible compared to the amount of heat dissipated down through the Si substrate/package lid and into the heatsink -- and you only have to do a quick estimate of the relative thermal resistances and cross-sectional areas to realise this.

So adding cobalt on the bottom couple of via/interconnect layers will reduce the heat flux through the BEOL from negligible to even more negligible -- do you see the point? Measurements are not needed to "prove" this because the numbers make it obvious.

You can call this "thermal gasket effect" or anything else you want, but in real life it has no significant impact in high-power devices.

 

[IanD]

That viewpoint misses a lot.

Intel's process technology development pipeline is quite long, xxnm process development program, itself years long, is preceded by pathfinding and component research.

So ask yourself: if Intel observes today slower cobalt wires, what speed did they observe in their pathfinding work?

You're misunderstanding what I said; it's not that cobalt has got slower since Intel did their early pathfinding work (when they decided to use cobalt), it's that copper has got faster as people have found ways of reducing the effective resistivity of copper at very fine pitches (or reducing the resistivity increase which amounts to the same thing).

If you look back four years IMEC were saying that cobalt had a speed advantage at these geometries, now they're saying it doesn't any more and in fact there are no cases where it's the best choice -- copper is still best down to some point, below that ruthenium is better, and cobalt is never the best choice.

Ruthenium does have safety issues, but then so do many of the other materials used for IC fabrication and these have been dealt with -- it's not as if living breathing humans get anywhere near the wafers nowadays, if they did the yield would be zero for everybody. Supply is by far the biggest problem if Ru becomes widely used for ICs, world reserves are estimated at 5k tonnes (12t mined per year) compared to 7Mt for Co (100kt mined per year) and ~1Gt for Cu (20Mt/year). All of which just increases the pressure to stay with Cu and try and improve it further instead of switching interconnect material...

One penalty of being very early into a market is that the goalposts may have moved by the time everyone else joins in, especially if there are big delays in getting to market; this is what has happened with Intel vs. the foundries and Cu/Co.

 

[DrizztVD]

Fact inspired..... good one. I don't particularly care for Charlie. I read his site when I first started blogging and found him to be wrong as much as right, especially when it comes to the foundries. I did meet him onetime and found him to be an okay guy except that he spends a lot of time looking at his feet when talking.

The financial side is not my area of expertise but I do know people who are much more qualified than Charlie. Scott Jones for example. I would call Scott fact based versus fact inspired though.

Your debate style varies between ad hominem attacks to calls to authority. And it decidedly lacks a logical formulation going from premise to link to conclusion. The former are varying forms of fallacy, whereas the latter is the only form of rationality allowed in a strict sense in WUDC. I suggest you study argumentation theory because your response inspires little confidence beyond pseudo-rationality applicable to a very narrow range of speciality. Meaning that, while you may be right, your argument does not convince a truly objective entity that assumes no prior knowledge of the debate or debaters. The pitfall in a continued reliance of such methods of validity-testing is likely to rapidly lead to self-delusion. i.e A says x is correct, because A is always correct B says x is correct, C says x and y is correct, A thinks C is always correct (but is not), therefore B also thinks x and y is correct, but y is incorrect and B has no way of knowing because Bs validity is checked against A only. - This is a summary of how your argumentation fallacies lead to the wrong place. The corollary is that C thinks z is incorrect, A thinks C is always incorrect (but is not), therefore B now wrongly thinks z is incorrect.

Another way to understand the call to authority fallacy you use to debate is to see that it creates a circular inference. A thinks B is correct who thinks C is correct who thinks A is correct. Now add a slight perturbation to the links between each entity (due to communication imperfections for instance), and you get a circular and unstable feedback system because none of the entities rely on outside verification (truly objective analysis) and each just defers objectionality to the entity to their left, based on the assumption that that entity will analyse correctly. Except, when all entities defer analysis, no analysis is done and the reality of A, B, and C rapidly diverges from objective truth. A closed community is highly susceptible to this effect and, the more closed it is, the faster this effect happens, always.

 

[DrizztVD]

The thing is, predicting that a process will be late is not a big deal because most of them are. We put our best foot forward and hope for a smooth ramp but rarely is that the case. Which is why TSMC does the half nodes that share the same fabs (20nm/16nm, 10nm/7nm).

So you're saying that being three-four years late is not a big deal? How does that compute? Thing is, Charlie predicted that Intel 10nm is a mess, not just that it's late, which is two different things.

I did say skip 10 and jump to 7 and GF did just that. TSMC could not because of Apple and the process learning that is required.

That appears to be a strong contender for a strawman argument. raghu78 argued mostly for the severity of the Intel 10nm process delay, and your response choses to ignore that mostly and focus on a tangential issue which is what Intel should have done. That is not the burden of proof here - which revolves around the current reasons for the Intel 10nm delay and the current blocks to commercial viability. What should have been done is water under the bridge. Intel has already done 10nm low volume, the only remaining contention is whether they should go to high volume or to shift focus to 7nm without bringing 10nm to mass volume. That is not the same thing as jumping 10nm entirely.

 

[IanD]

Apart from the technical challenges with EUV (including pellicles, which ASML may think can be done without but right now nobody agrees except for vias/contacts) the real elephant in the room is equipment supply.

To make EUV economically viable it has to be used for high-volume production (e.g. Apple Axx), but this needs a *lot* of EUV machines (which will also drive the cost down). The rate of EUV scanner production is heavily constrained at the moment especially by the optics, Zeiss can't make good ones fast enough to keep up with demand (a multilayer EUV mirror is very different to immersion optics). And by the time EUV really hits (hopefully) big volumes the next-generation high-NA anamorphic optics will be needed, which is an even bigger challenge.

So "EUV in MP" doesn't just mean that it meets the cost and throughput targets to make the foundries happy to use it, it also means they need to be able to get their hands on enough EUV equipment to support the really big-volume applications which demand EUV -- because otherwise the cost won't be competitive with multipatterning. This seems to me to be a bigger challenge than just getting the throughput/uptime/quality to introduce EUV into MP in the first place.

Does anyone have any insight on this? How many EUV scanners would be needed to support big-volume smartphone AP production at 5nm or below, and how fast can ASML/Zeiss churn them out in the near future?

 

[raghu78]

You're misunderstanding what I said; it's not that cobalt has got slower since Intel did their early pathfinding work (when they decided to use cobalt), it's that copper has got faster as people have found ways of reducing the effective resistivity of copper at very fine pitches (or reducing the resistivity increase which amounts to the same thing).

If you look back four years IMEC were saying that cobalt had a speed advantage at these geometries, now they're saying it doesn't any more and in fact there are no cases where it's the best choice -- copper is still best down to some point, below that ruthenium is better, and cobalt is never the best choice.

Ruthenium does have safety issues, but then so do many of the other materials used for IC fabrication and these have been dealt with -- it's not as if living breathing humans get anywhere near the wafers nowadays, if they did the yield would be zero for everybody. Supply is by far the biggest problem if Ru becomes widely used for ICs, world reserves are estimated at 5k tonnes (12t mined per year) compared to 7Mt for Co (100kt mined per year) and ~1Gt for Cu (20Mt/year). All of which just increases the pressure to stay with Cu and try and improve it further instead of switching interconnect material...

One penalty of being very early into a market is that the goalposts may have moved by the time everyone else joins in, especially if there are big delays in getting to market; this is what has happened with Intel vs. the foundries and Cu/Co.

You are making a very good point . TSMC and GF have continued to work on extending Cu to 5nm and even 3nm . IMEC too published a paper recently on extending Cu to 3nm .

Semiconductor Engineering .:. Dealing With Resistance In Chips
Press Release - Imec Extends Damascene Metallization Towards the 3nm Technology Node

 

[DrizztVD]

Does anyone have any insight on this? How many EUV scanners would be needed to support big-volume smartphone AP production at 5nm or below, and how fast can ASML/Zeiss churn them out in the near future?

Afaik, the target for 2019 is about 20 for the year, but production engineers think 10-15 is the max doable. That leaves 20 EUV machines for 2020, depending on how the increased investment in Zeiss works out to ramp up even further. The customers also need to be willing to accept failures on certain tests for this to be the case, since the machines are too complex to produce error-free for all test cases.

Samsung bought enough EUV equipment to start 7nm, but 8LPP is used likely because 7nm will not yet reach the volume required to transition fully to 7nm on all tape-outs. I'd expect 7nm to reach volume in 2019 as the light sources are upgraded and some new EUV machines are delivered. But, the industry will be constrained on EUV for the foreseeable future.

So "EUV in MP" doesn't just mean that it meets the cost and throughput targets to make the foundries happy to use it,

Cost cost cost. Everything is about costs. If you could buy a EUV machine that does 1 wafer/hr that cost $1 and was as big as a microwave, it would still make EUV viable. If you say 'enough' throughput' you actually mean 'overhead costs divided by number of chips produced is not cost effective'. Costs costs cost - that's all there is to it. The throughput on multipatterning is getting so bad that EUV throughput can cost 4-5x that of DUV and still be cost effective because the overheads will get paid when you look at total factory output. The lack of EUV equipment means that the cost for designing an EUV-based process is not justified when looking at the total factory output - the design costs are not absorbed.

If an engineer tells you "it's not possible", then respond with: "I'll pay you $1Billion if you did it" - and the answer stays the same, then only do you truly know the real answer. Engineers keep on thinking they should make binary decisions on technology. That is not their job. They should calculate what the costs would be if they moved heaven and earth to do something, and then tell management: "well, it will cost $50Billion according to my calculations to do it". Then management will look at return on investment and make a call.

 

[IanD]

I don't think anyone's disputing that for EUV to be used in real big-volume mass production it has to be cost-competitive with multi-patterned immersion -- hopefully cheaper, but certainly not more expensive, because lowering cost due to higher density is the only real reason to go to the next node nowadays since the power and performance improvements have slowed right down.

If we take TSMCs latest Fab 18 planned for 5nm which will end up at around 1M wafers/year, and guess at 30 EUV mask levels (entire FEOL + all fine-pitch BEOL -- is this a reasonable guess?) this needs around 4000 wafers/hour allowing for machine availability, which probably means that just this one fab will need the entire world supply of EUV steppers...

If anyone has better numbers I'd love to see them ;-)

 

[Scotten Jones]

You are making a very good point . TSMC and GF have continued to work on extending Cu to 5nm and even 3nm . IMEC too published a paper recently on extending Cu to 3nm .

Semiconductor Engineering .:. Dealing With Resistance In Chips
Press Release - Imec Extends Damascene Metallization Towards the 3nm Technology Node

My write up of imecs IITC paper comparing cobalt, copper andd ruthenium just went live here: https://www.semiwiki.com/forum/cont...er-cobalt-ruthenium-interconnect-results.html

When considering line resistance, via resistance and electromigration imec believes cobalt makes sense below 40nm.

 

[Scotten Jones]

I don't think anyone's disputing that for EUV to be used in real big-volume mass production it has to be cost-competitive with multi-patterned immersion -- hopefully cheaper, but certainly not more expensive, because lowering cost due to higher density is the only real reason to go to the next node nowadays since the power and performance improvements have slowed right down.

If we take TSMCs latest Fab 18 planned for 5nm which will end up at around 1M wafers/year, and guess at 30 EUV mask levels (entire FEOL + all fine-pitch BEOL -- is this a reasonable guess?) this needs around 4000 wafers/hour allowing for machine availability, which probably means that just this one fab will need the entire world supply of EUV steppers...

If anyone has better numbers I'd love to see them ;-)

Hi Ian

No EUV use in the FEOL at 5nm, SAQP for Fins and SADP for Gate, I thought we might see EUV for fin cuts but I am told not at 5nm. EUV LER isn't anywhere good enough for transistor formation. EUV for 3 contact layers, 3 metal layers and 3 vias or something like that. So probably around 9 EUV layers at 5nm.

ASML shipped 12 EUV tools last year with the 250 watt source plus several machines from 2016 are getting the 250 watt upgrade. 20 tools should ship this year and I still believe that number, 30 are due to ship in 2019 and 40 in 2020.

Samsung has around a dozen tools with over half 250 watt sources, TSMC and Intel each have around 5 tools and GF has 2.

I believe around 1 million wafers will get processed in 2019 with some EUV layers and around 2 million wafers in 2020.

You can read my write up on the EUV ramp here: https://www.semiwiki.com/forum/content/7249-iss-2018-impact-euv-semiconductor-supply-chain.html

The doses being used are higher than I assumed in my original calculations but ASML has further increased the throughput since then.

Scott

 

[count]

On EUV at 5nm - I'd expect 7nm to be a long life node, and many companies will likely end up skipping 5nm altogether. So I'd expect volumes at 5nm to be maybe a bit lower than expected. Then at 3nm, which may well be the last node shrink that makes any economic sense, there will be tool reuse from 5nm. I think there may be tightness in the EUV tools market like many are suggesting, but I think demand for 5nm will be low and between that, a little more time and tool reuse for 3nm, the foundries should be able to get the tools they need.

 

[Daniel Nenni]

On EUV at 5nm - I'd expect 7nm to be a long life node, and many companies will likely end up skipping 5nm altogether. So I'd expect volumes at 5nm to be maybe a bit lower than expected. Then at 3nm, which may well be the last node shrink that makes any economic sense, there will be tool reuse from 5nm. I think there may be tightness in the EUV tools market like many are suggesting, but I think demand for 5nm will be low and between that, a little more time and tool reuse for 3nm, the foundries should be able to get the tools they need.

I agree completely, for TSMC. TSMC has mastered the half node approach with 20/16nm, 10/7nm, and 5/3nm is next. Apple will certainly use 5nm but it really depends on the PPA value proposition of 5nm. Maybe EUV can help push people to 5nm by reducing design complexity? It really is up to the big TSMC customers. The difference this time is TSMC 7nm+ (EUV). Will customers skip both 7nm+ and 5nm? Interesting wrinkle for sure.

 

[raghu78]

My write up of imecs IITC paper comparing cobalt, copper andd ruthenium just went live here: https://www.semiwiki.com/forum/cont...er-cobalt-ruthenium-interconnect-results.html

When considering line resistance, via resistance and electromigration imec believes cobalt makes sense below 40nm.

Scotten
There seems to be differing thoughts on the topic of Cu vs Co or Ru for BEOL at sub foundry 7nm nodes. IBM/GF seem to make a case that there is no crossover point where Co is better than Cu. IBM/GF made a presentation at VLSI 2017. I am only quoting wikichip's article which references that paper.

A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium – WikiChip Fuse

"Cobalt has shown superior EM and TDDB over copper at high-current low-cross-sectional wires which is one of the primary reasons Intel switched to Cobalt. What's more interesting is, at last year's VLSI Symposium, IBM/Globalfoundries reported that the thinnest possible Cu barriers can be achieved by using Cu with TaN/Ru barriers or tCoSFB (Through-Cobalt Self Forming Barrier). By the way, they also claim that Cu with tCoSFB has lower line R than even Co and Ru, meaning there is no cross-over point where Co would be better than Cu. But that seems to go against what Intel is doing with 10nm. It's unclear who is right. So there is clearly a fork in the road as far as interconnects go.

We do not know exactly where Ru was found (the info is reserved for TechInsights subscribers) but given everything discussed, we suspect Intel is using Ru/Cu wires for their Metal 2, 3, and 4 layers. This is likely done for the exact reason GlobalFoundries reported - create the thinnest possible barrier. It will definitely be interesting to see what the rest of the industry converges on."

GF continues to work on extending Cu for the BEOL by improving its performance

http://vlsisymposium.org/wp-content...018-VLSI-tip-sheet-combined-FINAL-4.17.18.pdf

"GLOBALFOUNDRIES will present their results on laser-induced grain growth withinCu interconnects. They demonstrate a 30% reduction in Cu line resistance, which deliversa 15% improvement in RC and improvement in IDsat of 2-5%. The performanceimprovement is concomitant with improved dielectric VBD and Cu EM reliability,without impact on ULK mechanical stability, thereby providing a path for Cuinterconnect extendability"

What are your thoughts on the BEOL candidates for 3nm node ? Do you think the industry will find ways to extend Cu or go with Co or Ru for metal layers at 3nm node.

 

[Scotten Jones]

Scotten
There seems to be differing thoughts on the topic of Cu vs Co or Ru for BEOL at sub foundry 7nm nodes. IBM/GF seem to make a case that there is no crossover point where Co is better than Cu. IBM/GF made a presentation at VLSI 2017. I am only quoting wikichip's article which references that paper.

A Look at Intel’s 10nm Std Cell as TechInsights Reports on the i3-8121U, finds Ruthenium – WikiChip Fuse

"Cobalt has shown superior EM and TDDB over copper at high-current low-cross-sectional wires which is one of the primary reasons Intel switched to Cobalt. What's more interesting is, at last year's VLSI Symposium, IBM/Globalfoundries reported that the thinnest possible Cu barriers can be achieved by using Cu with TaN/Ru barriers or tCoSFB (Through-Cobalt Self Forming Barrier). By the way, they also claim that Cu with tCoSFB has lower line R than even Co and Ru, meaning there is no cross-over point where Co would be better than Cu. But that seems to go against what Intel is doing with 10nm. It's unclear who is right. So there is clearly a fork in the road as far as interconnects go.

We do not know exactly where Ru was found (the info is reserved for TechInsights subscribers) but given everything discussed, we suspect Intel is using Ru/Cu wires for their Metal 2, 3, and 4 layers. This is likely done for the exact reason GlobalFoundries reported - create the thinnest possible barrier. It will definitely be interesting to see what the rest of the industry converges on."

GF continues to work on extending Cu for the BEOL by improving its performance

http://vlsisymposium.org/wp-content...018-VLSI-tip-sheet-combined-FINAL-4.17.18.pdf

"GLOBALFOUNDRIES will present their results on laser-induced grain growth withinCu interconnects. They demonstrate a 30% reduction in Cu line resistance, which deliversa 15% improvement in RC and improvement in IDsat of 2-5%. The performanceimprovement is concomitant with improved dielectric VBD and Cu EM reliability,without impact on ULK mechanical stability, thereby providing a path for Cuinterconnect extendability"

What are your thoughts on the BEOL candidates for 3nm node ? Do you think the industry will find ways to extend Cu or go with Co or Ru for metal layers at 3nm node.

Please post this comment on the IITC article and I will respond there, I think that makes more sense than in this thread.

 

[Arthur Hanson]

As an outsider, I appreciate the information on 3dXpoint and the INTC/MU relationship and the differences. Just from the conference calls, it feels like MU has a different path in mind. Any more elaboration would be appreciated. I know the buy out provisions are more than interesting between the two. Not your usual partnership.