Semiwiki on LinkedIn Semiwiki on Facebook Semiwiki on Twitter Register / Log in 
Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/index.php?threads/intel-10nm-process-problems-my-thoughts-on-this-subject.10535/page-7
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021370
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Intel 10nm process problems -- my thoughts on this subject

IanD said:
Nope, there are just more immersion layers in N5 because the process is more complex -- at 5nm all EUV layers are single-patterned.

The M1 multipatterning referred to is not because of double-patterned EUV, it's because of the 3:2 ratio between poly pitch (underlying cell) and metal pitch (port connections). This means there are (I think) 4 versions of each cell with different port positions and restrictions about which version of a cell can be next to which version of the adjacent cells, and the tools deal with this by using colouring.
Click to expand...

That's strange to call it multipatterning color assignment then. I had the impression no color is needed for single patterning? Color was only in the context of assigning different masks for different parts of the layout in the same layer.

The layer number difference also seems too much to be accounted for by extra metal, FEOL, etc. The graph looks closer to assuming 3 DUV masks removed per EUV layer, so about half the mask count (over 40 masks) involved.
 
Fred Chen said:
That's strange to call it multipatterning color assignment then. I had the impression no color is needed for single patterning? Color was only in the context of assigning different masks for different parts of the layout in the same layer.

The layer number difference also seems too much to be accounted for by extra metal, FEOL, etc. The graph looks closer to assuming 3 DUV masks removed per EUV layer, so about half the mask count (over 40 masks) involved.
Click to expand...

Whatever it's called, there's 1 EUV mask and the coloring is needed to fix the problem of metal/poly pitch mismatch and prevent the tools generating millions of DRC violations when they place and connect up to the cells. Same fix as metal coloring for dual-patterning, different reason. N7+ does the same thing since it also has 3:2 poly:M1 pitch ratio.

The number of masks replaced by 1 EUV mask differs from layer to layer, for example in N7+ 1 EUV mask replaces 4 or 3 or 2 immersion masks in N7, so savings could be between 1 and 3 immersion masks per EUV mask. If we take 2 as an average, 14 EUV masks in N5 would save 28 masks compared to N7, but it looks like there are about 25 extra immersion masks going by the total count. I asked the same question you did and TSMC told me that this was just due to increased process complexity, without giving a detailed breakdown.
 
Last edited:
IanD said:
Whatever it's called, there's 1 EUV mask and the coloring is needed to fix the problem of metal/poly pitch mismatch and prevent the tools generating millions of DRC violations when they place and connect up to the cells. Same fix as metal coloring for dual-patterning, different reason.

The number of masks replaced by 1 EUV mask differs from layer to layer, for example in N7+ 1 EUV mask replaces 4 or 3 or 2 immersion masks in N7, so savings could be between 1 and 3 immersion masks per EUV mask. If we take 2 as an average, 14 EUV masks in N5 would save 28 masks compared to N7, but it looks like there are about 25 extra immersion masks going by the total count. I asked the same question you did and TSMC told me that this was just due to increased process complexity, without giving a detailed breakdown.
Click to expand...

Thanks for clarifying. I still don't see why you need to put different colors on the same M1 mask for finding violations; they're going to keep their pitch locations on the mask regardless. In any case, the mask count, i.e., cycle time, is not reduced even with the EUV, and now more of the layers are obviously going to be slower with the EUV vs. DUV throughput and uptime.
 
Fred Chen said:
Thanks for clarifying. I still don't see why you need to put different colors on the same M1 mask for finding violations; they're going to keep their pitch locations on the mask regardless. In any case, the mask count, i.e., cycle time, is not reduced even with the EUV, and now more of the layers are obviously going to be slower with the EUV vs. DUV throughput and uptime.
Click to expand...

The vertical M1 locations are fixed, so are the poly locations, but they don't match each other. Now put a cell down (location locked to poly grid by transistors) and try and connect to it -- there's only a 25% (I think...) chance that all the hit points (metal connections) on the cell will line up with the metal grid, and they have to because you can't jog them. So you need different versions of each cell with differently positioned hit points for connecting to metal -- but how do the tools know which one to use? The solution is to colour the metal (on or off poly grid), and do the same with the cell hitpoints, and make sure they match. I think you need 4 versions of each cell (two colours of hitpoints, normal and flipped layout) but I'm not sure.

Yes, N5 is going to have longer TAT and more expensive than N7+ (which should have shorter TAT and about the same cost as N7). That's the reality of a more advanced process...
 
Last edited:
IanD said:
The vertical M1 locations are fixed, so are the poly locations, but they don't match each other. Now put a cell down (location locked to poly grid by transistors) and try and connect to it -- there's only a 25% (I think...) chance that all the hit points (metal connections) on the cell will line up with the metal grid, and they have to because you can't jog them. So you need different versions of each cell with differently positioned hit points for connecting to metal -- but how do the tools know which one to use? The solution is to colour the metal (on or off poly grid), and do the same with the cell hitpoints, and make sure they match. I think you need 4 versions of each cell (two colours of hitpoints, normal and flipped layout) but I'm not sure.
Click to expand...

I guess it is mainly unexpected to me because before there was double patterning the pitches did not match either but there was no coloring solution. So I only associated coloring with multipatterning, and the number of colors with the number of masks.
 
Fred Chen said:
I guess it is mainly unexpected to me because before there was double patterning the pitches did not match either but there was no coloring solution. So I only associated coloring with multipatterning, and the number of colors with the number of masks.
Click to expand...

Before double patterning there was also usually 2D metal, which allowed L-shaped connections to be made. Now metal is 1D with cut masks to section up tracks and is usually on a minimum pitch grid, there's no way to make such connections, the metal has to stay on the grid and directly land on the cell hit points.

With EUV and 3 metal tracks in the space of 2 poly tracks like N7+ and N5 the M1 coloring is not [mask A|mask B] but [on poly grid|off poly grid].

And don't get me started about the inflexibility of the layouts (and complexity of the rules) in these processes. Want to change the poly spacing -- nope, can't do it. But I want to get better contacts to the diffusion -- tough. How about moving these tracks apart to reduce capacitance -- nope, can't do that either. We spent weeks playing around with the layout of a single transistor to reduce access resistance and parasitic capacitance and improve performance at 40GHz, and basically the rules won't let you do almost anything you'd like to do... :-(
 
IanD said:
If you have a fab line it's difficult to run unless you have 1 EUV stepper (or 2 -- any integer works) per EUV layer -- for example how does having 5 steppers per 4 layers work? So if N5 has 14 EUV layers, I'd expect the TSMC 5nm fab to have at least 14 EUV steppers -- or given the availability, maybe a couple of spares so that 14 are in use and 2 undergoing maintenance at any one time. This would fit pretty well with the stated fab capacity if the source power is 300W.
Click to expand...

Semiconductor fabs don't work like that. In a semiconductor fab all the machines are not put in a long line. In order to do that you would also need to put all the machines for the intermediate steps like implants, etching. ... in a long line. Semiconductor fabs use lot based processing. A lot is a number of wafers that is moved to the right machine for the next process step. This movement is not a fixed route, e.g after machine X comes always machine Y.
All EUV machines will be able to perform all EUV layers; if one goes down or is in maintenance another machine can take over. It's a matter of priority which layer on which lot will be done first. Putting all machines in a long line would actually be a nightmare as each hiccup in one of the machines would stall production.
 
Last edited by a moderator:
Staf_Verhaegen said:
Semiconductor fabs don't work like that. In a semiconductor fab all the machines are not put in a long line. In order to do that you would also need to put all the machines for the intermediate steps like implants, etching. ... in a long line. Semiconductor fabs use lot based processing. A lot is a number of wafers that is moved to the right machine for the next process step. This movement is not a fixed route, e.g after machine X comes always machine Y.
All EUV machines will be able to perform all EUV layers; if one goes down or is in maintenance another machine can take over. It's a matter of priority which layer on which lot will be done first. Putting all machines in a long line would actually be a nightmare as each hiccup in one of the machines would stall production.
Click to expand...

Intel's SVG (DUV) fleet for 0.25 um was well over 100 tools.
 
Last edited:
So Charlie's saying 10nm is canned. Does that mean we're going straight to 10+ or instead a shift to 7? Is it metallization change or a lithographic change happening? Or is Charlie just going doomsday over nothing?
 
He responded
Update October 22, 2018@3:30pm: Intel has denied ending 10nm on Twitter. The full tweet is, “Media reports published today that Intel is ending work on the 10nm process are untrue. We are making good progress on 10nm. Yields are improving consistent with the timeline we shared during our last earnings report.” SemiAccurate stands by its reporting.
Click to expand...
 
I am not sure he should apply "good" to the progress they are making though if their end shipment schedule is unchanged.
 
10nm parts available in volume a year early; do you think Intel made a sudden fundamental milestone in yield? Would that be Cobalt or SAQP? Do you know if these parts are competitive? Maybe they snuck in some EUV! (haha). Snapping sounds negative.
 
Chipper said:
10nm parts available in volume a year early; do you think Intel made a sudden fundamental milestone in yield? Would that be Cobalt or SAQP? Do you know if these parts are competitive? Maybe they snuck in some EUV! (haha). Snapping sounds negative.
Click to expand...

Murthy implied no process changes (for 14nm and 10nm), targets are the same as previously defined.

"the power, performance, and transistor density targets... remain the same."

Intel says it “clearly underestimated the challenge” of 10nm, but claims 7nm is still on track | PCGamesN

"14 and 10nm are really about double patterning and cold patterning in the absence of EUV."
 
Last edited:
You must log in or register to reply here.
Back
Top