No, that's not what I said at all. I said 40nm-36nm is not equal to SADP-SAQP.
I keep bringing up Intel's 45nm process because it illustrates the trap of your assumption: you can't simply look at pitch and draw correct conclusion on that basis as to what patterning technique is used.
Besides, we know now that Intel had to resort to quintuple and sextuple patterning for 10nm from Krzanich during his last conference call, why do you prefer not to notice it? You fall in the trap of your assumption right there.
You can't rely on it. Relying on known pitch to draw conclusions about patterning technique is as misleading as Bohr's metric with regard to density -- it simply doesn't tell you what you really need to know, as in case of Intel it simply doesn't correspond to transistor density of their real products.
Actually in an earlier post you said:
"Regarding this note, 36nm vs 40nm is not the same as SADP vs SAQP. E.g. Intel went SADP on 45nm node, so for them 40nm-36nm transition would have been nothing more than 10% reduction with no changes in patterning technique."
Clearly you are saying Intel could continue to use the same technique for 36nm as for 40nm, they can't. 10% doesn't matter, the absolute pitch matters. You can do 40nm with SADP, you can't do 36nm with SADP and while that doesn't mean you have to use SAQP, but you have to use something other than SADP and from the Intel article we know they used SAQP.
Also Intel didn't use SADP on their 45nm node, it was LE2.
"Besides, we know now that Intel had to resort to quintuple and sextuple patterning for 10nm from Krzanich during his last conference call, why do you prefer not to notice it? You fall in the trap of your assumption right there."
In the Intel Q1 conference call BK said this:
"So think of them as improvements to the various edge stuff, the lithography stuff, thin cleans and things like that in order to really drive the multi-patterning and, in some cases, multi-multi-patterning, where you have four, five, six layers of patterning to produce a feature. It's really about that. They aren't necessarily around performance."
SAQP is a pitch quadrupling technique in one direction that uses one mask to form the mandrel for the spacers. In the orthogonal direction you have cut or block masks, sometimes a lot of them because you don't get pitch multiplication in that direction, if you have 3 or 4 or 5 cut/block masks it is still SAQP. I am not "not noticing it", I am using the generally accepted industry nomenclature. SAQP with 4 blocks masks is 5 total masks and with 5 block masks it would 6 total masks but is still SAQP.
"Relying on known pitch to draw conclusions about patterning technique is as misleading as Bohr's metric with regard to density -- it simply doesn't tell you what you really need to know, as in case of Intel it simply doesn't correspond to transistor density of their real products."
I actually didn't rely on the pitch to draw a conclusion on patterning technique, the patterning technique has been published.
In terms of the "Bohr's metric" comment you can't fairly compare processes based on transistors per die area unless the designs are the same. Since that is almost never the case it is the standard industry practice to use metrics like CPP x MMP, or CPP x MMP x Tracks or the "Bohr metric" I use. I don't claim the 'Bohr metric" is perfect and I also publish SRAM cell sizes to cover Cache but the metrics are the best available.
The whole compare transistor per die argument has been discussed on here before and this thread is already muddied enough.
