Intel 10nm process problems -- my thoughts on this subject

[Daniel Nenni]

Sounds like something Intel would want us to believe, however the product roadmap for 2019 paints a different picture

I understand that. I did not speak to the Intel marketing people so I am talking about what is technically possible. My hope is that the current Intel road map has lots of room for improvement. Let's not forget what happened at Intel 14nm. Not a smooth transition there either. Intel did fess up about the 14nm challenges after the fact and I'm hoping they will do the same with 10nm so we can all learn from it.

 

[Fred Chen]

What everyone seems to forget is SAQP in the FEOL and BEOL are completely different. FEOL is cut masks, SAQP with cut masks for fins is well established. In the BEOL you need SAQP with block masks and that is completely different and much harder! The first block mask etches off the layers you need for subsequent block masks so you have to put all the block masks on reverse toned and then reverse the whole thing at the end. SAQP in the BEOL is likely 3 or 4 block masks so really complex and I believe this is most likely Intel's yield problem in-line with their comments about lithography issues.

There was comment about how going 10% below 40nm shouldn't be a cliff but that is exactly what it is. SADP can do 40nm, at 39nm you are looking at SAQP (optical) or EUV, 40nm is literally a lithography cliff in cost and difficulty.

I had found out there are still ways to get below 40 nm pitch without SAQP or EUV, they are SADP extensions basically, e.g., US7846849B2 - Frequency tripling using spacer mask having interposed regions
- Google Patents or LELE followed by SADP.
The thing about the SAQP metallization is both metal and dielectric are shaped by spacers.

 

[IanD]

I conducted an interview with imec yesterday about their IITC paper and I will be writing it up shortly. From my interview, cobalt doesn't beat copper for line resistance until around a 12nm lines and that is equivalent to something like a 16nm or 18nm pitch (for low level interconnect the line is wider than the space), however you get better electromigration and lower via resistance. At the lower levels, via resistance is very important and the imec position is that cobalt becomes attractive around a 40nm pitch depending on your design. Intel's 36nm pitch and their need for high power may just mean their design goals are different than the foundries who are more focused on low power mobile, and therefore Intel concluded cobalt made sense for them.

What everyone seems to forget is SAQP in the FEOL and BEOL are completely different. FEOL is cut masks, SAQP with cut masks for fins is well established. In the BEOL you need SAQP with block masks and that is completely different and much harder! The first block mask etches off the layers you need for subsequent block masks so you have to put all the block masks on reverse toned and then reverse the whole thing at the end. SAQP in the BEOL is likely 3 or 4 block masks so really complex and I believe this is most likely Intel's yield problem in-line with their comments about lithography issues.

There was comment about how going 10% below 40nm shouldn't be a cliff but that is exactly what it is. SADP can do 40nm, at 39nm you are looking at SAQP (optical) or EUV, 40nm is literally a lithography cliff in cost and difficulty.

In terms of 10nm parts what I think Intel is doing is they are shipping small quantities of 10nm parts coming out of their D1X development fab in Oregon. 10nm is scheduled for high volume manufacturing in Fab 28 in Israel and that isn't on-line yet.

The industry position has shifted regarding Cu/Co fine pitch interconnect resistance in the last few years as people have found ways to further reduce the Cu resistance. When Intel made their decision to go with cobalt interconnect for 10nm (which must have been 3-4 years ago) the pitch threshold at which cobalt won out was considerably bigger than it is now, so a decision that now looks wrong (with the benefit of hindsight) was probably right at the time --though risky as the first adopter, but then a similar gamble with Finfet paid off massively for Intel and left the rest of the shocked industry scrambling to catch up.

SAQP in the BEOL is undoubtedly a nightmare -- not least for the design engineers and tools! -- which would be unacceptable to foundry customers, but presumably this pain was judged to be acceptable inside Intel in order to squeeze that little bit of extra performance/density out of the process (along with the quint/hex patterning in some layers which has been mentioned).

Whether the problem is cobalt interconnect or BEOL SAQP or quint/hex patterning, it seems that Intel took risks that nobody else did and this time (unlike FinFET) it didn't pay off.

 

[-AM-]

Yes, I acknowledged that cobalt is likely a serious problem for Intel 10nm. It just so happens the cobalt layers used SAQP (as announced) as published, which could have aggravated it, as you concur. Regarding the other answers:
- The ASML throughput announcement is under the condition of a nominal dose of 20 mJ/cm2, which is probably no longer used because of stochastic issues; that is one of the more severe EUV issues. The throughput of EUV is dependent on dose.
- The density metric is based on a weighted sum of logic cells (60% NAND and 40% flipflop), to allow easier comparison among companies, as Scotten mentioned. There is direct involvement of MMP and CGP and the number of tracks. The SRAM cell size doesn't seem to trace this metric. It's the denser component in the layout (memory instead of logic), and also very design-dependent (you have high-density and low-density versions), so it's more difficult to standardize for comparison. In any case among the three foundries, it is a few % difference. The logic density is also a few % difference among the foundries, so the point is EUV's use by Samsung did not help it get a clear advantage in density among companies.
- I brought up Samsung 7nm with EUV since it also seems to be on shaky ground, like Intel's published 10nm. The commonality is MMP below 40 nm. It can be discussed elsewhere as you wish.

Re. EUV: 20 mJ/cm² shot noise is generally considered as just acceptable, the problem arise with the use of 20mJ/cm² resists in hvm afaik. Besides, 30 mJ/cm² dose allows throughput in excess of 100 wph -- are you aware of this? Iow, there don't really seem to be severe roadblocks left for EUV, only issues with lwr, ler, uptime, actual total cost of running euv line, etc. Not saying they are all easy, just that the path to hvm is finally clear, and TSMC is starting EUV risk mfg this year as well and 5nm (which is probably EUV-only) risk mfg in H1'19.


Re density: what you say is that their 7nm demo does not show competitive transistor density. But do you realize that transistor density of their demo chip is in fact on the order of 200 Mtr/mm²?


Besides, Bohr's metric is quite misleading and shouldn't really be used. Time permitting, I will probably write a post on this subject to clear out the mess and stop propagation of this rather misleading means of comparison.


Re. Samsung: again, don't take their 36nm from 2016 IEDM paper as a final spec, they could have easily changed it, and their 7nm EUV is clearly not late as of now -- we will be able to make relevant judgment only around March 2019, and they still have half a year ahead to keep tuning resist and work on yield improvement before they start running production wafers for S10 closer to year end.


Actually, every time I point out to mistakes or inconsistencies in what you say you simply modify your argument to something different. This is not a good practice to discuss things.

 

[-AM-]

By the way, the "cobalt thermal gasket" issue which the OP keeps bringing up is a red herring -- in all high-power chips including CPUs >95% of the heat exits the back of the die (through the bulk silicon) to the heatsink, not up through the metal/dielectric interconnect stack. A higher thermal resistance cobalt metal stack has negligible effect on die temperature -- trust me, I've tried using this path to reduce Tj with copper interconnect and it simply doesn't work.

Do you realize that transistors are not the only source of losses, they do occur in the IC as well? So what happens when your thermal resistance between the source of losses and the cooler which dissipates most of them is 4x higher?

I actually do have very high respect for people sharing first-hand experience, but let me ask you: did you do actual measurements of die and IC temperatures -- all-copper IC vs CuCo stack? Did you run at least any simulations?

Because in case you didn't or miss that IC itself is a source of heat that must be dissipated, you're simply not in position to make such comments. Over at RWT some people had good fun at my findings, including the gasket effect, but as clues started coming in, the laughs died away, and none of those who had a good laugh are even seen anymore commenting on my posts.

By calling it "thermal gasket effect" I simply follow established tradition (skin effect, Miller effect, etc.). Naming it after myself is just too arrogant, but of course my ego would be very much pleased if the effect of using metal with low thermal conductivity in metallization stack on temperature fields in an IC gets named after the person who described it first.

Take it from me, if I had what it takes to do actual measurements to back my findings, I would have done so. Unfortunately I don't.

 

[-AM-]

The industry position has shifted regarding Cu/Co fine pitch interconnect resistance in the last few years as people have found ways to further reduce the Cu resistance. When Intel made their decision to go with cobalt interconnect for 10nm (which must have been 3-4 years ago) the pitch threshold at which cobalt won out was considerably bigger than it is now, so a decision that now looks wrong (with the benefit of hindsight) was probably right at the time

That viewpoint misses a lot.

Intel's process technology development pipeline is quite long, xxnm process development program, itself years long, is preceded by pathfinding and component research.

So ask yourself: if Intel observes today slower cobalt wires, what speed did they observe in their pathfinding work?

 

[-AM-]

There was comment about how going 10% below 40nm shouldn't be a cliff but that is exactly what it is. SADP can do 40nm, at 39nm you are looking at SAQP (optical) or EUV, 40nm is literally a lithography cliff in cost and difficulty.

Scotten, thanks for commenting here.

Regarding this note, 36nm vs 40nm is not the same as SADP vs SAQP. E.g. Intel went SADP on 45nm node, so for them 40nm-36nm transition would have been nothing more than 10% reduction with no changes in patterning technique.

 

[Fred Chen]

Actually, every time I point out to mistakes or inconsistencies in what you say you simply modify your argument to something different. This is not a good practice to discuss things.

I thought we agreed we could discuss Samsung 7nm elsewhere? The main reason I brought it up was to indicate the difficultiies that are generally occurring going below 40 nm MMP, similar to Intel 10nm.

I don't see any mistakes or inconsistencies in what I wrote, but just bringing in more information. The densities with or without EUV at this point at the leading edge are comparable. It's a judgement of the increased steps without EUV vs. the issues of EUV implementation. I had worked in the field before, and had been following EUV for over 20 years. We have seen the rise of multipatterning. There is a deep pipeline of unresolved fundamental EUV issues (too much for any given article to fully cover) which can easily stop it. I had covered only a few in some other threads in the forum.

 

[Fred Chen]

Besides Intel 10nm, GlobalFoundries 7nm also has some cobalt, but more limited to contacts and local interconnects (from Scotten's report and their paper) and without above-mentioned patterning peculiarities. It would be interesting to see how that pans out.

 

[-AM-]

I thought we agreed we could discuss Samsung 7nm elsewhere? The main reason I brought it up was to indicate the difficultiies that are generally occurring going below 40 nm MMP, similar to Intel 10nm.

I don't see any mistakes or inconsistencies in what I wrote, but just bringing in more information. The densities with or without EUV at this point at the leading edge are comparable. It's a judgement of the increased steps without EUV vs. the issues of EUV implementation. I had worked in the field before, and had been following EUV for over 20 years. We have seen the rise of multipatterning. There is a deep pipeline of unresolved fundamental EUV issues (too much for any given article to fully cover) which can easily stop it. I had covered only a few in some other threads in the forum.

By mistakes/inconsistencies I mean what I had to point out and the divertions:
- 36nm mmp (just early plans, we don't know if they were reviewed),
- Samsung's EUV process being "late" -- it's not, and it's not "marketing" -- they have about half a year ahead to keep fine-tuning resists etc. before they have to start production in time for S10 intro,
- their 7nm demo doesn't have "incompetitive transistor density" and there's a big difference between chip's transistor density (which, by the way, is ca. 200 Mtr/mm² for what they have shown, which is certainly not incompetitive) and use of Bohr's density metric, which yields ca. 100 Mtr/mm²,
- density as calculated using Bohr's metric is not directly related to resolution
- finally there is simply no factual evidence to conclude that Samsung's 7nm EUV is in serious danger in any regard. It may be, or it may be not -- we simply lack data to make any solid judgments in this regard.


But every time I point it out, your argument simply changes to something different instead of addressing the issue, that's what I mean. E.g. do you realize that Samsung's demo chip indeed has density of about 200 Mtr/mm² or not? Because there's a big difference between simply not realizing it or realizing full well, but saying something different instead.


Regarding transfer of the discussion, unfortunately I don't know yet how to transfer posts from thread to thread here and whether forum members can do it at all, so I need some learning to do.


PS Thanks a lot for thumbing-up my posts, I appreciate it.

 

[Fred Chen]

By mistakes/inconsistencies I mean what I had to point out and the divertions:
- 36nm mmp (just early plans, we don't know if they were reviewed),
- Samsung's EUV process being "late" -- it's not, and it's not "marketing" -- they have about half a year ahead to keep fine-tuning resists etc. before they have to start production in time for S10 intro,
- their 7nm demo doesn't have "incompetitive transistor density" and there's a big difference between chip's transistor density (which, by the way, is ca. 200 Mtr/mm² for what they have shown, which is certainly not incompetitive) and use of Bohr's density metric, which yields ca. 100 Mtr/mm²,
- density as calculated using Bohr's metric is not directly related to resolution
- finally there is simply no factual evidence to conclude that Samsung's 7nm EUV is in serious danger in any regard. It may be, or it may be not -- we simply lack data to make any solid judgments in this regard.


But every time I point it out, your argument simply changes to something different instead of addressing the issue, that's what I mean. E.g. do you realize that Samsung's demo chip indeed has density of about 200 Mtr/mm² or not? Because there's a big difference between simply not realizing it or realizing full well, but saying something different instead.


Regarding transfer of the discussion, unfortunately I don't know yet how to transfer posts from thread to thread here and whether forum members can do it at all, so I need some learning to do.


PS Thanks a lot for thumbing-up my posts, I appreciate it.

Thanks for bringing up the points. I probably jumped around too much in my response to fully and completely answer you. I was not aware my responses appeared not to concur in some areas.

Regarding the density metrics, I agree that Intel's proposed logic density metric would favor its position. It is used mainly because it is useful for including pitches (basically resolution) and tracks into the discussion. SRAM cell sizes could have different versions (low-density, high-density) from the same companies. The SRAM densities can be determined by six transistors/SRAM cell size, so they look very similar between GF, Samsung, TSMC, and are all over 200 Mtr/mm2, much denser than logic, using the proposed logic density metric. Yet despite process differences, still all very similar densities among the three (Intel seems to be off a little), I think we can all agree. Still, some assumptions had to be made here and there, for sure. Also, the published or announced pitches could be changed in later process versions. If we consider Intel as the odd one out, with its problems, then SAQP BEOL process is a low-hanging fruit, as well as contact over gate, and cobalt metal lines. Intel uses single dummy gate in its 10nm, which might be in line with a reported use of single diffusion break at Samsung's 7nm.

Yes, based on what we know of EUV, Samsung's schedule for 7nm in 2018 is at risk. Samsung had planned to insert EUV in 2014 for 2xnm, so it is part of an ongoing delay. The insertion point has always been slipping.

 

[DrizztVD]

- Samsung's EUV process being "late" -- it's not, and it's not "marketing" -- they have about half a year ahead to keep fine-tuning resists etc. before they have to start production in time for S10 intro,

Mr. Chen has confirmation bias opposing EUV, hence why I've also offered him proof of the accelerated timelines that EUV has shown and he seems to discard these facts in favour of his reticent "EUV will fail" narrative. - And I'm purely stating this as a fact to aid in understanding Fred Chen's diversions. Have no fear, Mr. Chen and the other 2% of knowledgeable people who are still negative of EUV are increasing likely to be proven wrong within the next 6 months. My speculation is that the primary advantage EUV displays that knocks the negatives down is the reduction in patterning variation. period.

 

[Fred Chen]

Mr. Chen has confirmation bias opposing EUV, hence why I've also offered him proof of the accelerated timelines that EUV has shown and he seems to discard these facts in favour of his reticent "EUV will fail" narrative. - And I'm purely stating this as a fact to aid in understanding Fred Chen's diversions. Have no fear, Mr. Chen and the other 2% of knowledgeable people who are still negative of EUV are increasing likely to be proven wrong within the next 6 months. My speculation is that the primary advantage EUV displays that knocks the negatives down is the reduction in patterning variation. period.

I remember we had an exchange regarding 8LPP timing. Yes, indeed it is a stopgap for 7LPP. I was voicing my surprise since 8LPP is based on quadruple patterning, and EUV was supposed to avoid it. If EUV was coming later this year, it was odd to see 8LPP appear.

I don't know if you have a basis for being optimistic on EUV other than what is reported in websites? The negative information is hidden behind publication firewalls. Where is the reported reduction of patterning variation?

 

[DrizztVD]

they are but victims of someone's decision to employ heterogeneous CuCo stack

I've suspected for more than a year already that someone high up at Intel is, in plain English, busy being a moron. This is clearly shown in the apparent 'dispute' that Micron and Intel have on the memory side on charge trap vs floating gate NAND, and someone at Intel is immovable on the subject to the extent that Micron severed the partnership to save themselves from Intel's moronicity [sic].

The first clue I got to this behaviour is in the language Intel started using regarding yields. They would repeatedly offer an explanation of "we need xx% on aspect yy of EUV before we will use it". The problem with such statements are that they reflect poor underlying engineering practice inherently. Engineers should never say, "when the performance reaches xx level then it will be ready to use and ONLY then". Instead, the language should be that "given parameters r,t,u, we estimate level xx to be the required performance for cost effective implementation". That statement indicates that the engineer knows his job - optimise the performance at a given cost level. Not "block an implementation because it doesn't reach my preconceived idea of good enough".

To respond specifically to the 10nm concerns, I see two major mistakes Intel made: 1) Not using their ASML partnership to get ahead of the EUV wave. 2) chasing the rabbit down the hole of IPC via power-hungry high-frequency cores to the neglect of pretty much all else.

The two work together to create their current problem. I should also state that saying "we don't have a suitable pellicle for EUV" I consider a non-engineering statement. Asml has repeatedly said "YOU DONT NEED A PELLICLE" but, especially for Intel, they refuse to listen. I know that Asml is developing a super-clean machine to try and force the industry to open their eyes and at least EXPLORE the possiblility of going pellicle-less.

Either way, the Cobalt issue then comes down to a max-frequency (timing) problem. I think 10nm just can't do 5 GHz, but Intel is unwilling to drop their turbo boost to say 4 GHz (3 GHz for laptop chips) because it would undermine their decades-long IPC rabbit-chasing endeavour. This also explains why TSMC and Samsung appear not to have 7nm problems like Intel does. The foundaries rarely go beyond 3 GHz, and GloFlo appears to have enlarged channels to do 4.5 GHz (perhaps). The reliability thing could be part of it, but, even if resolved, hits up against the laws of physics with IR drop and 4+GHz operation.

In conclusion, I would not want to work for Intel right now because it seems someone with years of experience is pulling rank and forcing (incorrect) decisions on younger engineers. Those decisions are coming back to haunt intel and I hope the offending person/persons gets booted soon. Virtually all scientists go from advocating visionary change to gatekeeping legacy decisions as they age. This is a vital change in role for a well-functioning society when in balance. Unfortunately, Intel appears to be leaning to gatekeeping far too much lately.

 

[DrizztVD]

I remember we had an exchange regarding 8LPP timing. Yes, indeed it is a stopgap for 7LPP. I was voicing my surprise since 8LPP is based on quadruple patterning, and EUV was supposed to avoid it. If EUV was coming later this year, it was odd to see 8LPP appear.

I still fail to see your logic on this. You're essentially saying "if EUV worked, then 8LPP would not be necessary". In a highly competitive environment where 6 months can mean the difference of $Billions in orders, it should be obvious why they deployed 8LPP to gain a marginal time advantage over competitors. Also, saying "quadruple patterning, and EUV was supposed to avoid it" is a little one-dimensional. EUV was supposed to enable avoiding many, many things, it's 10 years late after all.

This all comes down to the premise for engineering: is it an engineer's job to make binary decisions on technology or should an engineer seek to explore all viable options in an effort to discover an optimal (even if far from perfect) solution at that very moment in time? EUV is far from perfect at this time, but perfection itself should never be the reason for not deploying something - as Elon Musk reminds us so often.

 

[DrizztVD]

Can any of this impact 3D X-point? That seems to be another never-ending delay.

I don't think the x-point technology will be impacted simply because Micron is in on it as well. As far as X-point economics is concerned- I feel like someone at Intel should be kicked in the shin about it. Micron stated that Intel is NOT buying their share of X-point dies. I see this as a selfish mistake. Micron is incurring fab idle costs because of it and are currently a bit stuck because of this. - if they launch their own x-point then they will be competing with Intel, but the niche super-SSD market x-point currently targets is too small for two competitors and will likely just destroy both Intel and Micron X-point ASPs. Thus, Intel can charge more money for x-point as long as they have a monopoly on that level of performance, and should buy most or all of Micron's supply even if they do incur slightly more losses because of it. The sum result will be that Micron's balance sheet will look better because the fab idle costs will be removed and intel will gain a long-term brand reputation that they can later use to out-compete Micron. But, sadly, that is nowhere close to what Intel is doing, they're just playing defensive with their own balance sheet and not seeking to further the market as a whole short and long term by being more offensive.

 

[lefty]

There's quite a shocking article on Semiaccurate:
Intel's firing of CEO Brian Krzanich is a cover for deeper problems - SemiAccurate

First the 2019 date for the volume ramp was internally set at Q4/2019 or about 7 quarters away from that statement. Worse yet Intel internally had almost zero confidence they would hit that date, but this was not messaged at all to the analysts. If you understand semiconductor fabrication, you know it doesn't take 18-21 months to implement a known fix. Technically speaking the 2019 date was on the roadmaps and Intel is undoubtedly implementing things to fix the process, so we can't say they lied. Intent is a much grayer area that you can decide on for yourself.

It is SemiAccurate's informed technical opinion that Intel's 10nm process will never work at a financially viable level.

 

[Daniel Nenni]

It is SemiAccurate's informed technical opinion that Intel's 10nm process will never work at a financially viable level.

Hahahaha... What does that actually mean? Show us the math? Fake news.

 

[DrizztVD]

Hahahaha... What does that actually mean? Show us the math? Fake news.

Actually... read the article and it will show you the math. Personally, I see SemiAccurate as an opinion piece, but a fact-inspired one <g class="gr_ gr_31 gr-alert gr_spell gr_inline_cards gr_run_anim ContextualSpelling ins-del multiReplace" id="31" data-gr-id="31">non</g>e the less. Afaik they called the 10nm delay before even Intel management thought it would be required.

 

[benb]

Getting back to the discussion about cobalt, that was a fascinating list of problems and possible solutions, thank you AM. I don’t have that much to offer on the topic, other than this: BEOL has been dual-damascene (line and via formed at the same time, of the same metal) for as long as it’s been Cu. If the real advantage of Co is vias, I think it must just be too hard to separate vias and interconnects, so we get complete interconnects made of cobalt despite the detractors.

Ru is presented as an alternative but it has safety issues in the CMP module. RuO2 toxic gas forms during Ru CMP.