Introduction to Visualizer for the VHDL Users

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions …

Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Online - Jun 30, 2020 3:00 PM - 4:00 PM US/Pacific Register Overview In this session we provide an in-depth overview of Mentor’s recently launched Symphony Mixed-Signal Platform. Symphony is the industry’s fastest and most configurable mixed-signal solution …

Introduction to Visualizer for the VHDL Users

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions …

Addressing nm Mixed-Signal Verification Challenges with Symphony – Powered by the AFS Platform

Register For This Web Seminar Online - Jun 30, 2020 8:00 AM - 9:00 AM US/Pacific Register Online - Jun 30, 2020 3:00 PM - 4:00 PM US/Pacific Register Overview In this session we provide an in-depth overview of Mentor’s recently launched Symphony Mixed-Signal Platform. Symphony is the industry’s fastest and most configurable mixed-signal solution …

Tessent Visualizer – Increase your productivity with less time spent on DFT debug

Register For This Web Seminar Online - Jun 30, 2020 5:00 PM - 6:00 PM US/Pacific Register Online - Jul 1, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Designed for billion-gate designs, Tessent Visualizer is helping DFT engineers be more productive by addressing key challenges of the most time-consuming DFT debug tasks. Included …

Tessent Safety – Entering the Safety Ecosystem: a reference flow for automotive IC test

Register For This Web Seminar Online - Jul 7, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Industry-leading innovations in automotive electronics has immensely contributed in the development of advanced safety mechanism resulting in exponential growth in the amount of electronics that is being added while at the same time it continues to challenge …

Active Learning for Fast, Comprehensive SPICE Verification

Register For This Web Seminar Online - Jul 8, 2020 8:00 AM - 9:00 AM US/Pacific Register Online - Jul 8, 2020 5:00 PM - 6:00 PM US/Pacific Register Overview The scope of SPICE-level verification has increased massively with new requirements for safety critical applications, statistical timing characterization, wider FinFET voltage domains, and tighter product …

How to Use Calibre for Physical Verification

Register For This Web Seminar Online - Jul 8, 2020 10:00 - 11:00 Asia/Singapore Register Overview Physical Verification Overview Calibre Physical Verification General Introduction Basic Calibre Process Flow Calibre Hierarchical Processing How to Run Calibre DRC DRC Extension: eqDRC, Fast XOR and Antenna Checks Circuit Verification Process Flow How to Run Calibre LVS LVS Extension: …

From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology

Register For This Web Seminar Online - Jul 14, 2020 10:00 AM - 11:00 AM US/Pacific Register Overview Nowadays many ASIC and FPGA design projects start with a Simulink reference model. The traditional path from an abstract floating-point Simulink model to high-quality RTL code is long and often requires multiple manual coding stages, several designers …

Tessent DDYA – Improving the throughput of volume scan diagnosis by 10X using dynamic partitioning

Register For This Web Seminar Online - Jul 14, 2020 5:00 PM - 6:00 PM US/Pacific Register Online - Jul 15, 2020 8:00 AM - 9:00 AM US/Pacific Register Overview Learn how to achieve efficient utilization of hardware resources for volume scan diagnosis. This web seminar will be conducted by an expert in design-for-test and …

Valor Process Preparation Webinar – A Single Engineering Solution

Register For This Web Seminar Online - Jul 15, 2020 11:00 AM - 12:00 PM US/Pacific Register Overview Valor Process Preparation - A Single Engineering Solution for PCB Assembly and Test Electronics manufacturers typically have a silo system in which they perform the PCB assembly process engineering. The main challenge working with a separate system …