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From Simulink to High-Quality RTL using High-Level Synthesis — The Design Methodology
July 14, 2020 @ 10:00 AM - 11:00 AM
Register For This Web Seminar
10:00 AM – 11:00 AM US/Pacific
Nowadays many ASIC and FPGA design projects start with a Simulink reference model. The traditional path from an abstract floating-point Simulink model to high-quality RTL code is long and often requires multiple manual coding stages, several designers and multiple code bases to be maintained.
This process can be simplified by using Catapult High-Level Synthesis (HLS) along with a sophisticated workflow. The model transformation from Simulink to class-based C++ is much simpler than transformation to RTL because the abstraction level can be kept almost the same and the design hierarchy can be taken from the Simulink model hierarchy. Furthermore, by using a systematic data type definition scheme, the same functional C++ code can be used for both floating-point and fixed-point implementations. This reduces the number of code bases to be maintained down to two.
The whole process can be completed by 1-2 designers in a short time resulting in similar or even better power, performance and area metrics compared to a hand-coded implementation.
This webinar introduces a design methodology that will start from a flat floating-point Simulink model and step through to HLS generated RTL. All design steps including fixed-point conversion are described in detail.
What You Will Learn
- Simulink to RTL methodology overview
- Step-by-step walkthrough of the workflow:
- Preparing Simulink model for the transformation
- Converting Simulink design to HLS C++
- Validating Catapult HLS C++ model with Simulink
- Fixed-point conversion aka Quantizing HLS model
- High-Level Verification using Catapult Coverage
Who Should Attend
- Engineering Directors who need faster design cycles and lower verification costs than RTL design provides
- RTL Design and verification managers who need to improve team productivity
- RTL Designers concerned that RTL might no longer be enough to compete
- System Architects looking for optimal design partitioning for power, performance and area
- Algorithm Developers who are interested in HW bottlenecks in their algorithm