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Introduction to Visualizer for the VHDL Users

June 30, 2020 @ 8:00 AM - 9:00 AM

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Register For This Web Seminar

Online – Jun 30, 2020
8:00 AM – 9:00 AM US/Pacific


Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions and Coverage.

This session will introduce the Visualizer Debug Environment for VHDL and UVM.

What You Will Learn

  • Post-simulation and live-simulation debug
  • Driver tracing and X-tracing
  • Source code debug
  • Waveform debug
  • UVM Debug, including classes and transactions in the waveform
Rich Edelman
Rich EdelmanRich Edelman is a Verification Technologist specializing in helping customers adopt and deploy the UVM and OVM. Rich has worked in ASIC companies, EDA consulting, EDA start-ups, and 2 of the big three. Rich first got involved with the AVM while developing his “RPS training class”, which was an easy way for people to learn about the AVM. Rich’s verification interests range from DPI and transaction recording to register modeling, sequences and class-based debug. Rich has published many related conference papers, including a Best Paper on SystemVerilog DPI at DVCON, and various transaction recording papers with IPSOC. Rich received a BSEE, a BSCS and an MSCS from Washington University in St. Louis.

Who Should Attend

Design and Verification Engineers and Managers

Products Covered

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June 30, 2020
8:00 AM - 9:00 AM
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