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Tessent Visualizer – Increase your productivity with less time spent on DFT debug
June 30, 2020 @ 5:00 PM - 6:00 PM
Overview
Designed for billion-gate designs, Tessent Visualizer is helping DFT engineers be more productive by addressing key challenges of the most time-consuming DFT debug tasks. Included in the family of Tessent products, teams are able to make continuous progress with zero learning curve when switching tasks.
What You Will Learn
- How to increase your productivity by finding and tracing to objects in large cones of logic >100x faster than traditional tracing methods
- Using intuitive schematic features with full access to the tool’s data model attributes
- How to use the powerful table-driven search engine to debug test coverage and DRC violations faster
ABOUT THE PRESENTER
Jay JahangiriJay Jahangiri is a Product Manager for Tessent products at Mentor, a Siemens Business. He has nearly 25 years of experience in various DFT disciplines including ATPG, compression, BIST, and boundary scan. Jay worked as a DFT engineer for Texas Instruments and Raytheon prior to joining Mentor. He is the co-inventor of two US patents related to silicon test and holds a Bachelor of Science degree in Electrical Engineering and an MBA. Jay has published numerous papers and articles in the area of silicon test.
Who Should Attend
- DFT product engineers
- DFT product managers
- IC design engineers
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