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Webinar Series: Digital Implementation and Signoff

July 1, 2020

Webinar Series

Webinars are chosen during registration

Reduce Iterations, Achieve Faster Design Closure Time with Innovus Implementation and Tempus ECO Option

Wednesday, July 1, 2020
15:00 UKT / 16:00 CEST / 17:00 EEST/IDT / 10:00 AM EDT

Speaker: Thierry Sarrazin

The Cadence® Tempus™ Timing Signoff Solution is integrated with the Innovus™ Implementation System where it drives signoff-accurate and physically aware timing ECO that significantly shortens time to market, reduces power consumption, and eliminates wasteful timing margin. The Tempus ECO Option fixes setup, hold, glitch, and design rule violations. It can also optimize the design for dynamic power, static power, or total power. The Tempus ECO Option is physically aware and routing congestion aware and can be run on blocks and full chips, providing the fastest convergence. Attend this webinar to learn how the Tempus ECO Option can deliver signoff accurate design closure with fewer iterations.


  • Tempus ECO Option introduction and overview
  • Innovus integrated signoff closure flow
  • Power optimization and leakage recovery
  • Full chip-level, high-capacity ECO flow
  • Practical tips and tricks to deliver best PPA
  • Q&A

Achieving Voltage Drop Requirements Using Integrated Optimization and Signoff

Wednesday, July 8, 2020
15:00 UKT / 16:00 CEST / 17:00 EEST/IDT / 10:00 AM EDT

Speaker: Dirk Seidler and Giacomo Dimundo

During the past decade, a great deal of optimization technology has been developed to meet the timing and power goals of the latest SoC designs. However, implementing power distribution networks to meet voltage drop requirements has remained a largely manual task. With chips growing in size and complexity, and moving to the new FinFET process nodes, more automation is needed to meet the increasingly aggressive IR drop rules. During this webinar we will discuss the latest techniques for IR drop optimization within the Innovus Implementation System, such as IR-aware placement, clock tree synthesis, and power grid wire sizing, all based on the integrated Voltus™ voltage and power analysis and Tempus™

timing signoff engines. Attend this webinar to learn how to close IR drop constraints using an IR-aware implementation flow.


  • IR drop analysis and optimization introduction
  • Early IR drop analysis
  • IR drop optimization technology
  • Integrated voltage and timing analysis for true signoff results
  • Q&A

Addressing the Signoff Crisis with Tempus Power Integrity

Wednesday, July 15, 2020
15:00 UKT / 16:00 CEST / 17:00 EEST/IDT / 10:00AM EDT

Speaker: Thierry Sarrazin and Bertrand Genneret

As designers push high-performance operating frequencies at advanced nodes, IR drop poses a significant obstacle to ensuring silicon reliability. Despite well-margined methodologies, no robust approach was available to effectively measure and resolve the impact of IR drop on circuit performance prior to tapeout. Tempus Power Integrity introduces an integrated IR drop/STA solution combining the accuracy and speed of Tempus STA with Voltus IR drop analysis. Coupled with Innovus Implementation and Tempus ECO Option’s powerful IR avoidance and fixing capabilities, Tempus Power Integrity enables engineering teams to sign off the highest performing designs with utmost confidence.


  • Fundamental challenges in advanced-node IR drop analysis
  • Tempus Power Integrity for true timing signoff
  • IR drop fixing with Tempus ECO Option
  • Customer case studies
  • Q&A

How to Leverage Cadence Online Support to Your Advantage

Wednesday, July 22, 2020
15:00 UKT / 16:00 CEST / 17:00 EEST/IDT / 10:00 AM EDT

Speaker: Mukesh Jaiswal

Cadence Online Support is a powerful platform to find tool support information and ask questions of the experts. By understanding how to get the best from Cadence Online Support, you will be able to use the tools more effectively. This session is primarily a hands-on demo of the Cadence support portal, where we will introduce the self-help capabilities and explain tips and tricks to get the best out of Cadence Online Support. Attend this webinar to learn how to use Cadence Online Support to your advantage.


  • Introduction and benefits of the support portal
  • Different access methods, browser, mobile app, and tool GUI
  • Home page and features
  • One-stop solution – Product pages
  • Finding information quickly using the Search facility
  • Case submission and feedback
  • Q&A

Full Flow Power Analysis and Optimization

Wednesday, July 29, 2020
15:00 UKT / 16:00 CEST / 17:00 EEST/IDT / 10:00 AM EDT

Speaker: Dirk Seidler and Andreas Koke

Power analysis and optimization is critical throughout the lifecycle of a program. Effective power analysis requires different strategies and tools depending on where you are in that lifecycle. Achieving the lowest power product requires optimizations that start at the system architecture and continue to microarchitecture and through to implementation and signoff. Functional stimulus plays a critical role in achieving this goal. We will cover the Cadence solutions for power analysis and optimization starting with early system-level analysis, through RTL-level architecture/microarchitecture, low-power implementation, and finally to silicon signoff. Cadence tools covered include Palladium® Dynamic Power Analysis, Joules™ RTL Power Estimation Solution, Stratus™ High-Level Synthesis Solution, Genus™ Synthesis Solution, Innovus Implementation Solution, and Voltus IC Power Integrity Solution.


  • Power overview – Impact of architecture/microarchitecture and functional stimulus
  • Architecture
  • High-level synthesis
  • Using emulation to drive power exploration
  • RTL power estimation and exploration
  • Microarchitecture
  • Selecting the best functional stimulus to drive optimization
  • Activity-driven optimization during synthesis
  • Implementation and signoff
  • Q&A
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