03 Mar 2020 - 05 Mar 2020 Fountain Hills, AZ, USA Join Cadence in Booth 42 at the International Microelectronics Assembly and Packaging Society (IMAPS)’s 16th annual Device Packaging Conference. The show is a major forum for the exchange of knowledge and provides numerous technical, social, and networking opportunities for meeting leading experts in these …
Integrated Circuit packaging has always been integral to IC performance and functionality. An IC package serves many purposes: (1) pitch conversion between the fine features of the IC die and the system level interconnection, (2) chemical, environmental and mechanical protection, (3) heat transfer, (4) power, ground and signal distribution between the die and system, (5) …
Double data rate (DDR) synchronous dynamic random-access memory (SDRAM) is the common type of memory used as RAM for almost every modern processor. With DDR memory interface voltages decreasing, speeds increasing, and timing/power budgets being squeezed, design qualification using the latest memory interfaces is no small challenge. Join Cadence Training and Srdjan Djordjevic, Sigrity Expert …
Continue reading "Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level"
Integrated Circuit packaging has always been integral to IC performance and functionality. An IC package serves many purposes: (1) pitch conversion between the fine features of the IC die and the system level interconnection, (2) chemical, environmental and mechanical protection, (3) heat transfer, (4) power, ground and signal distribution between the die and system, (5) …
Date: Tuesday, June 14, 2022 Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may accidentally lead …
Continue reading "Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows"
EMEAI Session Date: Tuesday, June 14, 2022 Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may …
Date: Thursday, June 16, 2022 Time: 11:00am - 12:00pm (PDT) Overview System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, …
Continue reading "Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows"
Date: Tuesday, September 20, 2022 Time: 10:00 - 11:00 (CEST) Electromigration (EM) impacts design reliability, causing failures over time. That is why it’s important to analyze both the power mesh and signal wires to check that the average, rms, or peak currents will not lead to a permanent failure. Learn how the Cadence Voltus IC Power …
Continue reading "CadenceTECHTALK: Preventing EM Failures in IC Designs with Signoff Analysis"
Accelerating Innovation in Photonic IC Design Why Attend? Photonics and photonic IC technologies are crucial to support rapidly evolving internet, healthcare, mobility, and security needs. Driven by data communications, photonic ICs are moving rapidly from the laboratory to mainstream and fueling a wave of innovations and product introductions. Join our Photonic Symposium to hear about …
