Webinar: Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

Double data rate (DDR) synchronous dynamic random-access memory (SDRAM) is the common type of memory used as RAM for almost every modern processor. With DDR memory interface voltages decreasing, speeds increasing, and timing/power budgets being squeezed, design qualification using the latest memory interfaces is no small challenge.

Join Cadence Training and Srdjan Djordjevic, Sigrity Expert and Sr Principal Application Engineer, for our free one-hour webinar, Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level, where you will learn how to:

• Minimize DDR supply and DC drop at the PCB/package level
• Obtain the required DDR supply impedance profile over frequency, low enough and resonance free
• Perform SSN simulation of a DDR bus using power-aware IBIS models
• Plus Q&A

Date and Time

Wednesday, March 18, 09:00 GMT / 10:00 CET / 14:30 IST / 17:00 CST

To register for the “Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level” webinar, use the REGISTER button and sign in with your www.cadence.com account (email ID and password) to login to LMS.

Then select “Request” to register for the session.

Once registered, you’ll receive a confirmation email containing all log-in details.

If you don’t have a www.cadence.com account, please contact us at training_germany@cadence.com

Please Note:

• Registration closes Tuesday, March 17.
• Space is limited—if you register, please plan on attending.

For questions and inquiries, or issues with registration, reach out to us:

Europe, Middle East, and Africa: eur_training@cadence.com
India – Vishwanath K
Asia Pacific – Cathy Li