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CadenceTECHTALK: Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows – EMEAI

June 14, 2022

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EMEAI Session

Date: Tuesday, June 14, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

System designers face increasing challenges to meet technical specification and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continue to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, disjointed design tools and flows provide a serious risk for product failure.

With the Virtuoso® Layout Suite EXL, Cadence provides a comprehensive platform for analog- and RF-centric systems that allows IC and package co-design in the context of each other. Edit-in-Concert design technology provides an unmatched capability to mitigate this risk and to increase efficiency.

Cadence’s Virtuoso platform provides advanced physical implementation flows for system design. IC designers can now take advantage of an existing package developed in Allegro® Package Designer Plus and continue the design in the Virtuoso Layout Suite EXL (enablement) and to reliably manage design changes in either Virtuoso or Allegro (ECO flows) environments.

Join us for this one-hour webinar to learn how to:

  • Use an initial SiP file from Allegro Package Designer to enable IC-package co-design in the Virtuoso platform
  • Keep in synch the SiP database and OpenAccess database in the Virtuoso platform
  • Modify a system design in the Virtuoso platform and incrementally update the corresponding SiP file
  • Review and accept/reject updates to the initial SiP file in Virtuoso platform


Claudia Roesch

Product Engineering Director, Cadence


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