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Increase Efficiency and Reduce Risks with IC and Package Co-Design Flows

June 16, 2022

Date: Thursday, June 16, 2022

Time: 11:00am – 12:00pm (PDT)


System designers face increasing challenges in meeting technical specifications and time-to-market requirements. While process nodes continue to shrink, the complexity of packages continues to grow. Large pin counts of flipped and rotated ICs may accidentally lead to I/O misalignment between die and package. Consequently, disjointed design tools and flows create a serious risk of product failure.

With the Virtuoso® Layout Suite EXL, Cadence® provides a comprehensive platform for analog- and RF-centric systems that allows IC and package co-design in the context of each other. Edit-in-Concert design technology offers an unmatched capability to mitigate this risk and increase efficiency.

The Virtuoso platform provides advanced physical implementation flows for system design. IC designers can now take advantage of an existing package developed in the Cadence Allegro® Package Designer Plus, continue the design in the Virtuoso Layout Suite EXL (enablement), and reliably manage design changes in either Virtuoso or Allegro (ECO flows) environments.

Join us for this one-hour webinar to learn how to: 

  • Use an initial SiP file from the Allegro Package Designer to enable IC-package co-design in the Virtuoso platform
  • Keep the SiP database and OpenAccess database in synch in the Virtuoso platform
  • Modify a system design in the Virtuoso platform and incrementally update the corresponding SiP file
  • Review and accept/reject updates to the initial SiP file in the Virtuoso platform


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