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System-in-package (SiP) designs for high-performance computing (HPC), high-speed networking, and AI applications are extremely complex. To achieve maximum performance without exceeding tight thermal and power constraints, these chips must be designed within the context of the package and the overall system. Ansys 2.5D/3D-IC multiphysics simulations for prototyping and signoff offer a complete methodology for analyzing …
Date: February 23, 2021 Time: 9:00 PM PST *This event will be broadcasted at 9:00 p.m. PT. To attend at 10:00 a.m. PT, please register here The next generation of processor cores such as the latest Arm® cores continue to get larger and more complex with challenging power targets. To achieve these targets, addressing power integrity …
February 24, 2021 9 AM EST / 2 PM GMT / 7:30 PM IST Venue: Online Ansys Minerva, powered by Aras, is the next generation simulation process and data management solution, fusing simulation and optimization to product lifecycle processes across the enterprise. Minerva boosts engineering productivity by democratizing simulation and enhancing collaboration between designers and …
Traditional FPGA programming models and hardware description languages are not intuitive to many software developers. And even if they are, using them for iterative algorithm development is time consuming. This webinar demonstrates how to streamline the process. Read More If you develop for field-programmable gate arrays (FPGAs), you’re likely familiar with the hours-long experience of …
Digital event | February 24, 2021 | 10:00 AM PST Synopsys is the world's leading provider of solutions for designing and verifying advanced semiconductor products. Accelerating Semiconductor Design & Verification on Azure Cloud presents a unique opportunity to accelerate the design and verification process of silicon chips using cloud computing. Learn how to bring your …
Time: 11:00 AM – 12:00 PM (PT) Abstract: Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification …
February 25, 2021 1 AM EST / 6 AM GMT / 11:30 AM IST Venue: Online Traction motor design is a key component in the electric vehicle/hybrid electric vehicle (EV/HEV) development process. Designing a highly efficient and cost-effective traction motor is challenging. It is a true multiphysics problem, requiring precise attribute balancing across all the …
Overview Your designs are getting bigger and your embedded software is growing exponentially. Yet, your development schedules are shrinking, and you must complete your projects earlier. Consequently, new tools are needed to address these ever-growing challenges. Although widely used for early software development, FPGA-based prototyping has the reputation of being difficult to do. The Cadence® …
Managing the relationship between hardware and software during system design is challenging. Complexities in both the hardware domain and software domain mask configuration issues and unfortunately do not get caught — until it is too late. Join me and Vishal Moondhra, VP of Solutions, for our webinar tomorrow as we discuss: How you can improve …
Managing the relationship between hardware and software during system design is challenging. Complexities in both the hardware domain and software domain mask configuration issues and unfortunately do not get caught — until it is too late. The hardware register definition has dependencies for embedded software designers. As a result, the software team must wait for …
Join us: BLT is co-organizing this free, live online training event with Xilinx Customer Training and other Xilinx Authorized Training Providers. The two day event includes live instruction, optional labs, and a drawing for a grand prize. Course: Designing with the Versal ACAP: Architecture & Methodology In this virtual, special event, you will be introduced …
Overview: Join this webinar to learn how Visual Design Diff helps analog/mixed-signal designers using the Cadence Virtuoso platform to manage ECO’s & conduct design reviews more efficiently. VDD gives design and layout engineers the power to quickly compare two versions of a schematic or layout by graphically highlighting the differences directly in the design editor. …
February 27, 2021 1 AM EST / 6 AM GMT / 11:30 AM IST Venue: Online The potential hazard resulting from uncontained turbine engine rotor blade failure has always been the long-term concern of each aero engine manufacturer, and to fully contain the failed blades under critical operating conditions is also one of the most …
