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Addressing Power Integrity with a Fast and Easy Signoff Ready Methodology for Next-Gen. Arm® Cores (APAC)
February 23 @ 9:00 PM - 10:00 PM
Date: February 23, 2021 Time: 9:00 PM PST
*This event will be broadcasted at 9:00 p.m. PT. To attend at 10:00 a.m. PT, please register here
The next generation of processor cores such as the latest Arm® cores continue to get larger and more complex with challenging power targets. To achieve these targets, addressing power integrity at the very end of the place & route step can result in late-stage ECOs and/or change to power grid strategy severely impacting the design schedule. In this Synopsys webinar, Synopsys experts will demonstrate a fast and easy-to-deploy Redhawk-Fusion and IC Validator in-design flow using Synopsys Fusion Compiler™ that leverages machine learning to achieve power targets on an Arm® Cortex® -A78 core in 5nm. Techniques such as Dynamic power shaping (DPS), IR aware placement, IR aware CCD, IR aware ECO, and Power grid augmentation (PGA) will be discussed.
Shankar Vellanthurai is a member of technical staff in the Arm Solutions Group (ASG). He works closely with Synopsys R&D to deploy new technologies and methodologies for high-performance Arm processor cores. Shankar has over 15 years of experience in the EDA industry at Cadence, Mentor, and now Synopsys. His primary focus is on synthesis, place & route, formal verification, and low power. Shankar holds an MSEE from Mississippi State University.Share this post via: