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Overview: Having difficulties in keeping track of changes to schematics and layouts in Cadence Virtuoso? In this webinar we will show you a methodology that engineers have been adopting to reduce inefficiencies and become more productive and increase throughput. Sign up for this webinar here What you will learn: Revision control with release and …
Stargazing quality KPIs across your factories This webinar will occur twice on the following dates: Tue, June 16, 2020 9:00 AM - 10:00 AM PDT GMT-7 (Suitable for attendees from USA and Europe) Thu, June 18, 2020 3:00 PM - 4:00 PM GMT+8 (Suitable for attendees from Europe and Asia) Please register for the date and time that works best for you. Register now! Come join our webinar and learn how to … Use LineWorks SPACE to automate and …
Security concerns permeate our digital lives. From online financial or personal data transactions, to automobile control and even election tampering, protecting access has become a critical necessity for almost all applications. With semiconductor hardware forming the foundation of modern electronic systems, a hack here can be disastrous. Protecting hardware against the myriad of potential vulnerabilities …
To run the real-world workloads on cycle-accurate hardware simulation framework is one of the essential tasks in the system-level validation before silicon tape-out. S2C introduced Prodigy Cloud System recently in the response to meet challenging targets. It is equipped with scalable FPGA capacity using the largest FPGA devices for multi-billion gate SoC design and verification. …
Use LineWorks SPACE to automate and standardize Quality KPI reports
Streamline your Quality KPI reporting and reviewing processes
Use LineWorks SPACE Dashboard to review your factory Quality KPIs
Stargaze your Quality KPIs across all factories using LineWorks STARGATE
Between factories, visualize and compare your processes, technology, equipment types, and more...
Identifying glitches and revealing the extra power they consume require special attention to cell delays and wire delays. To enable earlier and more frequent analysis, physical-and-timing-aware glitch power analysis is needed throughout the flow from RTL to Signoff. In this webinar, we review the glitch power challenges facing SoC designers and the key technologies that …
Overview: As geometries of integrated circuits get smaller and complex, electrostatic discharge (ESD) and Parasitic related design issues become prevalent. In this webinar we will show you a few methodologies to help reduce the design cycle by identifying ESD protection schemes in your netlist and assist in the verification of the point-to-point parasitic resistance between …
Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible, and at the lowest costs. Designers must verify and characterize their IP’s sensitivity to random parametric variations in the manufacturing …
If you are designing high-performance computing and networking SoCs for hyperscale data centers, then you require IP that enables large amounts of data to travel at very fast rates. Whether …
In the emerging era of large scale SoCs comprised from complex IP, typically designed for AI and automotive applications, designers must embrace an innovative approach to overcome numerous safety and …
Accurately estimating power for your vision SoC can make the difference between success and a multi-million dollar failure. Estimating power can be fairly straightforward for a RISC processor, but today’s vision SoC designs include neural networks with intense computation requirements making accurate power estimation much complicated. How can a designer have confidence in the power …
Closely monitoring Intellectual Property brings unmatched insights into the rapidly evolving and complex microLED competitive and technology landscape.
