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WEBINAR: Optimize SoC Glitch Power with Accurate Analysis from RTL to Signoff
June 23 @ 10:00 AM - 10:30 AM
Identifying glitches and revealing the extra power they consume require special attention to cell delays and wire delays. To enable earlier and more frequent analysis, physical-and-timing-aware glitch power analysis is needed throughout the flow from RTL to Signoff. In this webinar, we review the glitch power challenges facing SoC designers and the key technologies that enable strong correlation between early glitch power analysis and final signoff. SoC designers will gain the insights they need to: • Identify which nets have glitches and how many • Filter data to understand and rank the severity based on glitch duration and power consumption • Remove glitches, recover power, and identify the critical windows for hand-off to glitch-aware implementation, ECO, and IR drop analysis
• Patrick Sheridan, PrimePower Product Marketing, Synopsys
• Ashwin Sudhakaramenon, PrimePower Application Engineer, Synopsys
Patrick Sheridan is a member of Synopsys’ Signoff marketing team, responsible for PrimePower power analysis solutions from RTL to Signoff. He has 25+ years of experience in the marketing and business development of high technology software and hardware products for Silicon Valley companies, joining Synopsys in 2010 with a focus on virtual prototyping and emulation. Pat has a BS in Computer Engineering from Iowa State University.
Ashwin Sudhakaramenon is an Application Consultant on Synopsys’s North America Signoff team. Ashwin is responsible for timing and power signoff solutions. He has 10+ years of experience in EDA and has worked on multiple complex designs in emerging technology nodes and is an expert in developing efficient signoff methodologies. Webinar Organizers: SemiWiki.com and Synopsys