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RISC-V Formal Verification for ISA Compliance

July 7, 2020 @ 10:00 AM - 11:00 AM


RISC-V is an open standard instruction set architecture introduced in 2010. It has experienced exponential growth in recent years, enabling users to design custom processors more quickly and cost effectively to meet today’s demand for more technological innovations in the CPU, GPU, AI, ML spaces.

However, verification of the processor to find all corner-case bugs from the architectural and microarchitectural levels pose a tremendous challenge for dynamic simulation and emulation. Formal verification is known for its ability to prove the absence of bugs as well as find those complex corner-case bugs.

In this webinar, we will present a solution powered by a unique combination of Synopsys VC Formal apps and Axiomise’s RISC-V ISA formal solution enabling fast corner-case bug hunting, and exhaustive proofs of bug absence obtaining ISA compliance for RISC-V.

Dr Ashish Darbari is the founder and CEO of Axiomise. He has been actively using formal methods for over two decades with expertise in theorem proving, model checking, and equivalence checking.  Ashish loves sharing the joy of formal verification and has trained more than 150 engineers across the world.  A keen innovator in formal verification, Ashish has 24 US, UK, and EU patents and 32 peer-reviewed papers in formal verification.  He has a Doctorate in formal verification from the University of Oxford, and a Masters in CS from Germany. He is a Fellow of IETE and British Computer Society.

Xiaolin Chen is a Director of Program Management in the VC Formal AE team at Synopsys. She has been focusing on formal technology many years, working with customers to explore opportunities where formal technology can be best suited to solve verification problems. She leads a team of VC Formal AEs to provide guidance, training and technical assistance to customers as well as Synopsys field and design teams in driving formal technology deployment. Prior to joining Synopsys, she also worked as a verification engineer. Xiaolin has a MS in Electrical Engineering from California State University, Northridge.

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