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Mentor Graphics @ SEMICON West 2014

Mentor Graphics @ SEMICON West 2014
by Daniel Nenni on 07-04-2014 at 10:00 pm

Mentor is again the most represented EDA company at SEMICON West this year. I strongly advise Cadence and Synopsys to get more involved because EDA may be where electronics begins but semiconductor manufacturing makes all of our hard work come true, absolutely. Paul McLellan, Beth Martin, and I will be blogging live, I hope to see you there!

My good friend Steve Pateras is up first. I worked with Steve at LogicVision, which is one of Mentor’s most profitable acquisitions of all times I’m told. Steve is a great guy (very approachable) so don’t miss this one if you are even remotely involved in silicon test:

Ensuring High Defect Coverage of FinFET Based Designs

Steve Pateras
Marketing Director Silicon Test
Mentor Graphics

Abstract: The semiconductor industry is ramping deployment of FinFET transistors. These devices provide important benefits such as lower static leakage leading to lower power ICs, and high drive currents enabling faster switching at lower supply voltages. FinFETs however represent a fundamental change to the underlying structure of the transistor resulting in an impact on the IC design and manufacturing flows. In particular, FinFET critical dimensions are for the first time significantly smaller than the underlying node size, leading to a growing concern over increased defectivity levels and therefore test quality and cost.

This presentation will introduce the concept of Cell-Aware test, a transistor-level test methodology that overcomes the limits of traditional stuck-at and transition fault models and associated test patterns by targeting specific shorts and opens internal to each standard cell, resulting in significant reductions in defect (DPM) levels. This technique is used to specifically model and target leakage and drive strength related transistor defects that are likely to be common in FinFET devices. The Cell-Aware approach requires only modest increases in test time despite significant improvements in defect coverage, making it a highly efficient and thus pragmatic solution.

Using a Gallery Concept to Optimize an EUV Flow

Dr. Fan Jiang
Product Engineer, Mask Synthesis Solutions
Mentor Graphics

Abstract: While there is debate about when extreme ultraviolet lithography will be ready for production, there continues to be active research and development aimed at improving every aspect of the EUV system, including optical system modeling and correction. Unlike today’s ArF (λ=193nm) lithography, proximity effects aren’t much of a problem to EUV lithography because the wavelength (λ=13.5nm) is much closer to the size of the design features. However, because EUV systems are completely reflective (i.e., uses mirrors instead of lenses) there are new effects that did not exist or were negligible before, such as shadowing and flare, that must be addressed. Associated with these new effects are a range of models and correction techniques used to make up for limitations and inaccuracies in the EUV system, just as there are in today’s lithographic flow. Our research into a variety of these EUV resolution enhancement technologies (RET) indicates the there are many possible combinations of techniques thatmust be considered to create a flow that is optimized for target accuracy and performance (runtime) objectives. To achieve the best flow for specific product lines, lithography engineers need to start with a comprehensive gallery of models and tools that address the various issues that arise in practical EUV flows. This presentation will discuss the specific challenges of reflective EUV systems and demonstrate the variety of modeling and correction techniques that can help engineers meet both accuracy and runtime objectives for their IC manufacturing flows.

The Next Generation Scan Test Diagnosis

Geir Eide
Product Manager
Mentor Graphics

Abstract: Layout-aware diagnosis represented a dramatic advance in digital semiconductor diagnosis software technology. With up to 85% reduction in suspect area and the addition of defect classifications, it cemented the position of diagnosis in use for defect localization, and paved the way for use of diagnosis in yield learning applications. In this presentation, we will present Root Cause Deconvolution (RCD), the next generation diagnosis technology that dramatically improves the resolution in diagnosis results. RCD performs statistical enhancement of layout-aware diagnosis results to identify the underlying root causes of failures. For instance, layout-aware diagnosis may point to a net segment that spans multiple layers as the possible location of an open defect. RCD narrows this result down to a specific VIA in this net segment. This dramatically reduces the FA cycle time by increasing the FA relevance and success rate. It also enables “virtual FA”, the ability to determine accurate defect distributions for a population of failing devices before any failure analysis is performed….

SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

lang: en_US

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