The VLSI Symposium on Technology & Circuits will be held in Hawaii from June 12th to June 17th. You can register for the conference here.
The tip sheet for the conference has been released and one thing that caught my eye is some data from the Intel 4 paper that Intel will be presenting at the conference.
Intel’s old roadmap had 14nm, 10nm and then 7nm processes with 7nm being the first EUV based process and providing a 2x density improvement over 10nm. Intel eventually updated their roadmap to be more consistent with the numbering scheme used by Samsung and TSMC.
Intel has several versions of their 10nm process, the original version (or two) and then the super fin and enhanced super fin versions. Under the new scheme Intel’s 10nm enhanced super fin version became Intel 7, and the former 7nm process was replaced by Intel 4.
Intel 10nm has a transistor density of approximately 100 million transistors per millimeter squared, that is consistent with the density of Samsung and TSMC’s 7nm processes. I also believe Intel’s enhanced super fin process has performance as good or better than either of the foundry 7nm processes. Renaming Intel’s 10nm enhanced super fin to Intel 7 is therefore a designation more consistent with the foundry numbers.
When Intel announced Intel 4 they said it would provide a 20% performance per watt improvement and a significant density improvement but they didn’t provide a number. I thought this might mean they were relaxing the 2x density improvement, but the tip sheet disclosed that it is still 2x relative to 7nm. This would put the density between TSMC’s 5nm and 3nm processes, so Intel 4 is once again a name consistent with the foundry naming convention.
Does this mean Intel 4 will be around 200 million transistors per millimeter squared? This is actually a less straight forward question than you might think. When companies disclose dimensions for their processes, they often disclose values that are smaller than what are seen in standard cells. For example, TSMC says their 7nm process has a 54nm contacted poly pitch (CPP) but our strategic partner TechInsights measured 57nm in standard cells on actual designs. When we characterize a process what we have standardized on is using the densest standard cell seen on an actual part (once parts are available for analysis). TechInsights first saw 10nm Intel parts in 2018 in what TechInsights referred to as generation 1.
Generation 1 had a 54nm CPP consistent with what Intel claims. TechInsights saw generation 2 parts in 2019 that also had a 54nm CPP (the fins were taller than generation 1 suggesting is was a new generation). When Intel introduced the super fin version of 10nm they added an optional 60nm CPP for high performance cells. TechInsights analyzed these parts (generation 3) and saw both 54nm and 60nm CPP cells. Based on our convention this still works out to approximately 100 million transistor per millimeter squared. Where this gets interesting is the recent analysis TechInsights did on the enhanced super fin process (10nm generation 4, now known as Intel 7). This process also has an optional 60nm CPP, but what is interesting is in the standard cell logic, TechInsights only saw the 60nm CPP, no 54nm CPP and a taller track height. This results in a calculated density of approximately 60 million transistors per millimeter squared. So is Intel 4 going to be 200 million transistors per millimeter squared (100 x 2) or 120 million transistor per millimeter squared (60 x 2)?
My belief is it will be 200 million transistor per millimeter squared but it will be interesting to see how much of an actual design utilizes that density.
There is more data in the tip sheet to help answer this. The tip sheet discloses that the CPP is 50nm and the minimum metal pitch is 30nm. Current leading-edge processes all use a single diffusion break so we will assume that here as well. The only remaining question is track height, if I assume a 1 fin per cell 5-track cell then the density is right around 200 million transistors per millimeter squared. A single fin cell would likely require aggressive performance enhancements to meet Intel’s performance requirements, there might also be other design-technology-co-optimization in the process. A 5-track cell is possible for FinFETs without Buried Power Rail so this could be a solution.
It will be interesting to see what other data is included in the full paper. The fact that Intel is giving this paper does add additional weight to Intel being on track to introduce Intel 4 late this year.
SemiWiki blogger Tom Dillinger will be attending the event so you can read more from him after the event.