What is this RISC-V thing, anyway?

Overview

Are you considering leveraging the cost saving benefits of RISC-V in your next design? The RISC-V processor architecture is revolutionizing the business model for deployment of architectures in the embedded systems marketplace. While the processor design is maturing rapidly, the RISC-V software enablement is in its infancy.  Microchip and Mentor Embedded have teamed up to bring you the hardware and runtime software insights you need to successfully develop and deploy RISC-V devices.

What You Will Learn

• How the RISC-V processor architecture is different from traditional processor architectures
• What impact this disruptive technology could have on your future projects
• The important steps to take when selecting runtime solution
• Key considerations for commercializing, customizing and supporting open source based toolchains for RISC-V

ABOUT THE PRESENTERS

Tim MorinTim Morin is currently a Technical Fellow at Microchip in the FPGA Business Unit.  Tim has over 30 years of experience in Marketing and Engineering within the Semiconductor and Defense industries. Over the course of his career Tim held numerous engineering, sales and marketing positions at Texas Instruments Defense Electronics Group, Atmel Corporation, Microsemi Corporation and now Microchip Corporation where he is responsible for defining and bringing new products to market for the FPGA Business Unit.

Jeff HancockJeff Hancock is a Senior Product Manager in the Embedded Platform Technology Business Unit of Mentor, A Siemens Business. Jeff oversees the Nucleus®, and Mentor Embedded Hypervisor runtime product lines, as well as associated middleware, and professional services.

Who Should Attend

• Design Engineer / System Architect
• Engineering Manager
• Embedded Software Engineer
• Executive / CTO
• Project Manager