Scalable NoC, SoC and associated Testbench generation using Defacto STAR

As part of the Mont Blanc 2020, European scalable, modular and power efficient HPC processor, ATOS designs and implements a NoC which includes NoC Xpoints, Protocol agents and system cache.

Our Network on Chip (NoC) is based on basic Xpoint modules which are connected to each other to make a scalable NoC. Each Xpoint module has:

4 internal CHI Interface (1 per direction) where all the Xpoint modules are connected to 2 End Points CHI Interface which are the entry/exit points of IPs on the System on Chip (Soc).

A CHI interface contains 4 channels interfaces: Request, Data, Snoop and Response. Each channel is fully configurable in each direction and is implemented with Configurable System Verilog Interface. This makes a lot of parameters to handle as we plan to implement an 8×8 NoC which includes 64 Xpoint modules with corresponding parameters set accordingly.

Defacto STAR tool is used to efficiently:

instantiate all the Xpoint modules with corresponding parameters

connect all the channels with corresponding System Verilog Interface

Connect the Error, status and configuration interfaces

Connect Protocol Agent on End Point interface (internally)

Create NoC entity

The main benefits to choose Defacto STAR is: NoC configuration change and RTL generation in seconds No need to develop our own tools NoC module will then be integrated at SoC level and connected to IPs delivered by Third-parties. We also use Defacto STAR tool to generate the SoC RTL and associated Testbench.

SPEAKER: Laurent Marliac obtained his engineer diploma in 2000 at the Polytech University in Clermont Ferrand in France. He is working on hardware design for now more than 20 years, in telecom, smartphones and High Performance Computing. His main activity and responsibilities are: Managing technical team: 6 people on 3 projects. Managing logic design: from Front-end to MiddleEnd (Check STA is clean for Synthesis: Topo, Quality check) Customer machines follow-up.