Webinar: Removing Custom Layout Bottlenecks in Your Schedule with Concurrent Editing

Overview

We have witnessed an exponential growth in the complexity of chips. Today’s SoCs combine so many functions that a large design team is required to create layouts of different blocks. In addition, current design data management and underlying Unix file systems limit only one person at a time to work on an individual cell-view, creating project bottlenecks. This sequential layout methodology challenges individual designers, affects productivity, and often impacts the tapeout schedule.

Using concurrent layout editing allows multiple designers to simultaneously work on the same design cell-view, eliminating layout bottlenecks. Working in parallel leads to faster turnaround time and a big boost in team productivity.

In this one-hour webinar and demonstration, part of our custom layout series, you will learn how you can use Cadence® Virtuoso® Layout Suite EXL to:

• Create multiple partitions in a design cell-view so multiple designers can work in parallel
• Distribute layout tasks for design-rule check (DRC) fixing, chip finishing, and routing
• Manage, review, and merge multiple partitions into original design cell-view

Date and Times

Select the time that works best with your schedule

Thursday, May 28

Option 1 (EMEA and India):       09:00 BST, 10:00 CEST, 11:00 IDT, 13:30 IST

Option 2 (North America):        11:00am PDT, 1:00pm CDT, 2:00pm EDT