Webinar: Implementing DFT in 2.5/3D designs using Tessent Multi-die software
February 9 @ 9:00 AM - 10:00 AM
Next-generation devices increasingly feature complex architectures that connect dies vertically (3D IC) or side-by-side (2.5D) so they behave as a single device. The new Tessent Multi-die software delivers comprehensive automation for the highly complex DFT tasks associated with these 2.5D and 3D IC designs.
Tessent Multi-die software automates the generation and insertion of IEEE 1838 compliant hardware, defining the IEEE test access architecture for three-dimensionally stacked or 2.5D side-by-side integrated circuits. This solution helps customers dramatically speed and simplify critical design-for-test (DFT) tasks for next-generation ICs based on these architectures.
Who should attend:
- DFT engineers
- Test engineers
- Senior DFT managers
- CAD directors
- Anyone who needs to investigate DFT for 2.5D/3D IC design
What you will learn:
- How Tessent Multi-die supports the IEEE 1838 standard, including how Tessent Streaming Scan Network (SSN) can be used as the Flexible Parallel Port (FPP) for the standard
- How Tessent tools can help with DFT implementation for 2.5D/3D ICs
- How interconnect boundary scan-based patterns between the dies can be extracted using Boundary Scan Description Language (BSDL) from individual dies for 2.5D designs. Plus, unified package level BSDL creation in both 2.5D/3D devices
- How IJTAG complements both 2.5D and 3D test
Product Manager – Tessent
Vidya Neerkundar is a Product Manager for the Tessent product family at Siemens Digital Industries Software. She has over 20 years of experience in various DFT aspects with respect to hierarchical flows and architectures including Scan, Test points, boundary scan. Vidya has worked as ASIC design engineer for Conexant prior to joining Siemens EDA. Vidya holds a Master of Science degree in Electrical Engineering.
Product Manager – Tessent
Joe Reynick is a Product Manager for the Tessent product family at Siemens Digital Industries Software, where his responsibilities include packetized scan and Tessent Multi-die support. Joe has more than 38 years of industrial experience in ASIC Design, DFT, IP, Test and EDA technologies.
Joe served as Director of DFT Solutions at eSilicon, a pioneer of the fabless ASIC and COT models, from 2001 to 2020. His role included building and managing the worldwide DFT team, as well as the silicon bring-up/IP verification labs. His responsibilities included several 2.5C/5.5D projects.
Joe developed his passion for DFT as a member of the technical staff at AT&T/Lucent Bell Laboratories with a focus in the areas of DFT, ASIC Design, Optoelectronics, Test and EDA from 1984 to 2001.