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Reducing Area and Power Consumption while Increasing Performance with Formal-based ‘X’ Verification
October 15, 2020 @ 8:00 AM - 9:00 AM
Register For This Web Seminar
8:00 AM – 9:00 AM US/Pacific
Whether you are designing an ASIC or FPGA, it is often beneficial to use as many non-resettable registers or flip flops as possible: such elements are often significantly smaller than their fully-resettable counterparts, consume less power, and have a higher operational frequency. But how can you conclusively determine the maximum number of these elements that you can safely use without risking the creation of harmful ‘X’ signal corruption that could lead to unpredictable behavior in silicon?
Fortunately, “there’s an app for that”: Questa X-Check is an automated application that uses formal algorithms under-the-hood to exhaustively root out ‘X’ issues; but you don’t need to know Formal to use it. In this webinar we will share a comprehensive static and formal-based methodology employing this app that enables design teams to root cause ‘X’ issues early in the RTL design process. Results from real world case studies of this flow will be included.
What You Will Learn
- A brief review of ‘X’ initialization, propagation, and corruption issues
- A Formal-Based ‘X’ verification flow
- A real world case study employing this exact methodology
Who Should Attend
Design & Verification Engineers & Managers and those interested in Formal Verification
Joe HupceyJoe Hupcey III is a part of the Mentor’s Product Management team for Design & Verification Technologies; based in Mentor’s office in Silicon Valley, CA. He is responsible for the Questa Formal product line of automated applications and advanced property checking. Prior to joining Mentor, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.
Ping YeungPing Yeung, Ph.D. is the Principal Engineer in Mentor, A Siemens Business. He has over 20 years application, marketing, and product development experience in the EDA industry, including positions at 0-In, Synopsys, and Mentor Graphics. He holds 7 patents in the CDC and formal verification areas.