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High-Performance PCIe 5.0 IP + VIP UVM Verification Environment (US)

October 15, 2020 @ 11:00 AM - 12:00 PM


Together with Aldec, PLDA and Avery Design Systems, we will present and demo our newest PCIe 5.0 IP + VIP UVM simulation and debugging environment. PLDA’s PCIE 5.0 XpressRich includes internal datapath automatic scaling, configurable pipelining, Rx stream mode for custom credit management, L1 PM substates, dynamically adjustable application clock frequency and clock/power gating. Avery’s APCIe-Xactor includes best-in-class Verification IP for PCIe GEN5, native SystemVerilog and UVM support, native randomization, layer wise protocol and debug tracker and 35+ callbacks for error injection. In Aldec’s Riviera-PRO you can run RTL simulation and debug, visualize simulation waveforms, view the graphical representation of the UVM components, objects and the transaction level modeling (TLM) connections, and as well as use code coverage to analyze the efficiency of the UVM tests for exercising various parts of the RTL code.



  • PLDA’s PCIe 5.0 XpressRich IP
  • Avery’s APCIe-Xactor VIP
  • UVM-based simulation with Riviera-PRO
  • Conclusion
  • Q&A

Presenter Bios:

Michal Pacula, Technical Support Manager, Aldec

Michal joined Aldec in 1998 and worked in a wide range of positions that include Application Engineer and SQA Manager responsible for Active-CAD, Active-HDL and Riviera-PRO products.  Michal’s practical experience includes Digital Design, Verification Methodologies and a deep understanding of HDL modeling. Michal graduated with M.S. in Electronic Engineering (EE) at the Silesian University of Technology in Gliwice, Poland.

Sampath Banka, Sr. Applications Engineer, PLDA

Sampath has over 12 years of experience in Design & Verification and over 7 years of experience in PCI Express IP cores Integration, Debug and Verification. He has worked with PLDA’s customers and PHY partners worldwide to help them with PHY interoperability, integration and debugging of PCIe Express based designs. Sampath holds a B.E in Electronics and Communications Engineering from Anna University, India and PGDVLSI from TIIT, San Jose.

Florentin Bosshard, Verification Engineer, PLDA

Florentin has been working at PLDA – High speed interconnect leader – for over 2 years now, as verification engineer. As responsible for verification of the PLDA PCIe IP product, he uses and develops several verification environments, including internal and VIP-based. He received his engineering degree in electronics and computer science from Polytech Grenoble, France.

Luis E. Rodriguez, Verification IP Solutions Manager, Avery

Over the past 15 years Luis has held roles in R&D development, managing teams as well as in customer facing projects and business development. He has worked on PCIe related products for most of his career, and participates in industry events and consortiums. He is currently chairing a subgroup of the CXL Compliance Workgroup.

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October 15, 2020
11:00 AM - 12:00 PM
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