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2.5D/3D IC Packaging Verification

November 6, 2019

Register For This Seminar

Mentor Office – Fremont – Aug 7, 2019 
10:00 AM – 3:00 PM US/Pacific
Session full

Mentor Office – Fremont – Oct 2, 2019 
10:00 AM – 3:00 PM US/Pacific

Mentor Office – Fremont – Nov 6, 2019 
10:00 AM – 3:00 PM US/Pacific


Do you want to find out, hands-on, how many of the leading fabless semiconductor companies are verifying their complex 2.5/3D heterogeneous and homogeneous package assemblies?  Here is your chance to meet our technical staff and ask your questions.  Come and see why fabless semiconductor companies are adopting this flow, irrespective of the Package layout tools they use.

What You Will Learn

You will hands-on drive the Mentor flow for Advanced IC Package assembly verification using Xpedition Substrate Integrator and Calibre 3DSTACK.  You will construct a 2.5D design in Xpedition Susbtrate Integrator and then drive Calibre 3DSTACK to perform complete DFM, LVS and LVL verification.

Chris Cone

Chris ConeChris Cone has been driving design and verification methodologies for innovative technologies at Mentor for over 14 years.  Prior to joining Mentor Chris worked in analog and mixed signal design on various physical interface standards including USB, 1394 and Spacewire-LVDS.  Chris Cone earned his BSEE and MSEE with emphasis in microelectronics design at the University of New Mexico.

Who Should Attend

  • IC Package designers
  • IC Designers responsible for package/IC verification
  • IC Verification engineers who use Calibre
  • IC Package architects responsible for package selection

Products Covered

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